A Nyquist-rate delta-sigma A/D converter

King, E.; Eshraghi, A.; Galton, I.; Fiez, T.S.

doi:10.1109/4.654936

Cited by 47 publications

(13 citation statements)

References 9 publications

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“…1(b). Each channel consists of an input sampling switch, a low-pass (bandpass) modulator, a low-pass (bandpass) digital filter, and an output sampling switch [4]. Rotary switches are used at the input and output of the A/D converter.…”

Section: Mathematical Descriptionmentioning

confidence: 99%

A time-interleaved parallel ΔΣD converter

Eshraghi¹,

Fiez

2003

IEEE Trans. Circuits Syst. II

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A new architecture for Nyquist-rate analog-to-digital (A/D) conversion is presented. The new architecture combines the concept of time-interleaved A/D converters with the 16 A/D converter. For every doubling of the clock frequency, the resolution of the A/D converter improves by bits, where is the order of the 16 modulators. The advantage of the time-interleaved 16 A/D converter is reduced complexity of the digital filters. Another feature of this architecture is that the linearity of the converters depends on the linearity of each channel and is independent of the number of channels. Index Terms-Analog-to-digital (A/D) converter, Nyquist rate A/D converter, parallel 16, time interleaved A/D converter.

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Section: Mathematical Descriptionmentioning

confidence: 99%

A time-interleaved parallel ΔΣD converter

Eshraghi¹,

Fiez

2003

IEEE Trans. Circuits Syst. II

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“…The circuit is comprised of four major components namely, a summing element, an analog In this chapter, DS modulators will be treated as oversampled converters. There have been techniques, however, such as the one described in [18], where DS modulators have been implemented in parallel, thus increasing the resolution of the converter and reducing its oversampling rate or completely eliminating it.…”

Section: The Basic Loop Dynamicsmentioning

confidence: 98%

Data Conversion

Rouphael¹

2014

Wireless Receiver Architectures and Design

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“…An area-efficient architecture [6] is developed by combining multiple DSMs in parallel, along with analog preprocessing of the input signal and digital post-processing of the output signals.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and implementation of low-oversampling delta sigma modulators for high frequency applications

Mathew

Karthik

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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The key factor making Delta-Sigma modulators (DSM) one of the most popular components in modern electronic circuits is its high linearity. This is achieved by using a high oversampling ratio which is unfortunately the limiting factor towards its application in high frequency circuits. The necessity of high processing speed and power, the increased cost and complexity and wastage of available bandwidth are some of the significant demerits of using a high oversampling ratio. This paper suggests that the delta sigma modulators require a high frequency processing and not high oversampling ratio. A parallel structure to perform the high frequency processing along with an adaptive method to improve the signal quality at the output is proposed. The suggested technique allows the simultaneous execution of fast and complex computations required for wireless systems. The analysis is performed using MATLAB simulations and the results claim a reduction in oversampling ratio by a factor of 16 while keeping the same signal to noise ratio. The proposed architecture is implemented on a field-programmable gate array (FPGA) board which is then validated with a code division multiple access signal. The output signal bandwidth is observed to be increasing four times without any increase in the sampling frequency.

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A Nyquist-rate delta-sigma A/D converter

Cited by 47 publications

References 9 publications

A time-interleaved parallel ΔΣD converter

A time-interleaved parallel ΔΣD converter

Data Conversion

Design and implementation of low-oversampling delta sigma modulators for high frequency applications

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