A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

Perrott, Michael H.; Huang, Yunteng; Baird, R.T.; Garlepp, B.W.; Pastorello, D.; King, E.; Yu, Qicheng; Kasha, D.; Steiner, Philip; Zhang, Ligang; Hein, J.P.; Signore, B. Del

doi:10.1109/jssc.2006.884391

Cited by 34 publications

(12 citation statements)

References 15 publications

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“…However, this results in low tracking capability and narrow capture range. Moreover, large capacitance is needed to achieve low cut off frequency, but it occupies a large layout area [18]. Since the noisy received data is directly induced to the analog components, it increases jitter.…”

Section: Strong Noise Immunity Cdrmentioning

confidence: 99%

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A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver

Kosuge

Okada

Taguchi

et al. 2016

IEEE Trans. Circuits Syst. I

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A 280 Mb/s non-contact in-vehicle LAN system using electromagnetic clip connectors is presented. The bidirectional transmission line coupler based electromagnetic clip connector, which can be used to make local area network connections similar to clips, suppresses the signal reflections on the bus enabling 280 Mb/s data rate which is 7 times faster than the state-of-the-art in-vehicle LAN transceiver. Since all modules are connected with the shortest distance, this connection system can reduce wire harness weight by 30%. Forward error correction is done by N -x Manchester encoding on the transmitter side and majority voting on the receiver side. High noise immunity is achieved through synchronous receiving by the digital clock recovery circuit which is robust against noise. Communication tests were conducted at 280 Mb/s with 10 transceivers fabricated in 65 nm CMOS technology connected by a 10 m unshielded twisted pair cable. Evaluation of the bit error rate and radiation spectrum confirmed that the ISO specifications concerning electromagnetic susceptibility and the CISPR ones concerning electromagnetic interference are satisfied.

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Section: Strong Noise Immunity Cdrmentioning

confidence: 99%

“…In this work, the reference clock was generated by receiver side phase locked loop (PLL), which uses a low frequency global clock signal to eliminate frequency mismatch. This global clock can be removed by using a frequency recovery circuit [18]. Fig.…”

Section: Strong Noise Immunity Cdrmentioning

confidence: 99%

A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver

Kosuge

Okada

Taguchi

et al. 2016

IEEE Trans. Circuits Syst. I

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show abstract

“…4 phases for the data sampling and the other 4 phases for the edge detection. The 8 early/late data from the PDs are inputted to the decimation circuit [6] to vote UP/DN direction for the counter. The FSM block controls enable timings of the loop (i.e.…”

Section: Receiver Circuitmentioning

confidence: 99%

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

Lee

Kim

Son

et al. 2014

IEICE Electron. Express

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This paper presents a low-power half-rate clock-embedded transceiver architecture that employs quarter-rate multiplexing/de-multiplexing circuit technique, low-Vdd current-mode driver topology embedding halfrate clock, and multi-functional injection-locked oscillator (ILRO) for a digital clock and data recovery (CDR) design. The whole transceiver circuit was simulated in 65 nm CMOS process and its feasibility was proved successfully operating at 10 Gb/s across a band-limited channel. The achievable power efficiencies of the receiver and transceiver were 0.7 mW/Gb/s and 1.1 mW/Gb/s respectively.

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“…The phase detector is implemented as a linear Hogge structure [20], the charge pump schematic is shown in Fig. 17(a), consuming 300 A, and the loop bandwidth is chosen 2 MHz range to avoid using large external capacitor.…”

Section: F Baseband Sampling and Clock Generationmentioning

confidence: 99%

A 90 nm CMOS Broadband Multi-Mode Mixed-Signal Demodulator for 60 GHz Radios

Chuang

Yeh

Barale

et al. 2010

IEEE Trans. Microwave Theory Techn.

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In this paper, a low-power high-speed fully integrated mixed-signal quadrature demodulator with an embedded multi-gigabit modem in 90 nm CMOS technology is presented. A wide dynamic-range automatic gain control (AGC) is implemented to avoid clipping distortion experienced by the baseband ADCs. By reusing the power detector circuit within the AGC, analog signal processor is introduced to recover OOK modulated signals up to 2.5 Gb/s for an additional power consumption of 7.5 mW. Integrated with ultra-low-power, 3 mW, 3 GS/s, 3-bit ADCs and high-speed digital modem, the system requires neither external synchronization controls nor processing to demodulate BPSK modulated signals up to 3.5 Gb/s and DBPSK modulated signals up to 1.3 Gb/s. The baseband modem incorporates a mixed-signal, timing-recovery loop to sample the symbols at the optimum SNR based on a high-speed Gardner timing-error detector for an additional power consumption of 14 mW. The analog front-end consists of IQ mixers, a 13 GHz QVCO, frequency synthesizers, and a baseband AGC for an overall power consumption of 52 mW. The entire receiver chip occupies an area of 1.275 1.19 mm 2 . To the best of authors' knowledge, this demonstrates the maximum throughput at the minimum power budget and highest level integration among all published wireless multi-gigabit, multi-mode, mixed-signal CMOS receivers.

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A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

Cited by 34 publications

References 15 publications

A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver

A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

A 90 nm CMOS Broadband Multi-Mode Mixed-Signal Demodulator for 60 GHz Radios

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