Parallel delta-sigma A/D conversion

Abstract

This paper presents an architecture wherein multiple delta-sigma modulators are combined so that neither time oversampling nor time interleaving are necessary. For a system containing M Pthorder delta-sigma modulators, approximately P bits of accuracy are gained for every doubling of M . Thus, the resolution gained by combining M delta-sigma modulators is approximately the same as that with the same modulator with an oversampling rate of M. Measured results from a 16-channel parallel delta-sigma A/D converter composed of second-order delta-sigma modulators verify the theory and demonstrate that this architecture retains much of the robustness of the individual delta-sigma modulators to non-ideal circuit behavior. I. The Parallel AX A/D Converter ArchitectureThe parallel delta-sigma (IIAE) A/D converter architecture is shown in Fig. 1 [1 ,2]. The analog input z(n) is simultaneously applied to M modulators each followed by a conventional delta-sigma modulator. The AC modulator outputs are then filtered, demodulated and summed together to produce a single digital output sequence. In the c,onventional AC A/D converter both the signal and quantization noise pass through the same filter and therefore, both are filtered by the lowpass decimation filter, Fig. 2(a). In contrast, the IIAX A/D converter filters out much of the quantization error contributed by the AX modulators without filtering the input signal and without oversampling, Fig. 2(b). I e o ( n J I Hadamard sequence is referred to as Hadamard modulation. The Hadamard modulation is especially well suited for implementation since it consists solely of plus and minus ones. Thus depending on the value of the Hadamard sequence, the analog input signal and the digital output sequence are either passed or inverted.Figure 2: The signal and quantization signal paths for (a) the conventional delta-sigma modulator and (b) the parallel delta-sigma modulator.For a given number of channels (M), filter length and A E modulator, the power 'of the overall quantization error component can be determined using Fig. 3. For example, for a thiry-two channel II A E A/D converter with third-order AX modulators, and filters of length-190 or greater, Fig. 3 indicates that P, is 81 dR below A2 where A is the quantizer step size and P, is the. power in the quantization. To calculate the minimum number of bits, R, that a iiniform quantizer A/D converter would require to achieve the same mean squared A/D conversion error as the IIAE A/D converter, we use the approximate formula [5] Figure 1 : The parallel delta-sigma architecture.where 7 is the maximum absolute value of the IIAC modiilator input sequence. For A = 1 and 7 = 0.3, the converThe sequences u,(n), 0 5 T 5 M -1, are referred to sion accuracy of the IIAE A/D converter for the example as Hadamard sequences and the process of multiplying by a above corresponds to about 11 bits. 23.3.1 503 IEEE 1994 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-1886-2/94 $3.00 0 1994 IEEE

A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

“…The advantage of using this architecture is that while keeping many of the attractive properties of the delta-sigma architecture, oversampling is not required [40]- [41]. Therefore, these structures can be implemented with higher conversion speeds.…”

Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel -Modulators

“…Obviously, the decimation can be performed before the modulation, as shown in Figure 5(b), if the index of the modulation sequence is scaled by a factor of L. Considering the equivalent system in Figure 5(c), it is apparent that the downsampling by L can be moved to after the scalings by b k,l if the delay elements z −1 are replaced by L-fold delay elements z −L . The system may then be described as in Figure 5(d), where P k (z) is defined by (5). However, the outputs are taken from every Lth row of P k (z), such that the first output y k,L−1 mod M (m) is taken from row L, the second output y k,2L−1 mod M (m) is taken from row (2L − 1 mod M) + 1, and so on.…”

“…One way to reduce the operating frequency is to use several modulators in parallel, where a part of the input signal is converted in each channel. Several flavors of such ΣΔ-ADCs have been proposed, and these can essentially be divided into four categories: time-interleaved modulators (TIMs) [3,4], Hadamard modulators (HMs) [4][5][6][7][8], frequency-band decomposed modulators (FBDMs) [4,9,10] and multirate modulators based on block-digital filtering [11][12][13][14]. In the TIM, samples are interleaved in time between the channels.…”

A Wide-band 2-path cross-coupled sigma delta ADC

“…• Modulation based sigma delta modulators modulate and demodulate the input and the output of each path, respectively, with a certain function, [5]- [9]. The output of each path is then filtered to generate the digitized signal.…”