An amorphous indium gallium zinc oxide (a‐IGZO) layer is deposited on very thin conductive amorphous indium zinc oxide (a‐IZO) thin film to demonstrate high‐performance, coplanar thin‐film transistors (TFTs) with dual‐channel oxide semiconductor architecture. Based on material properties, a conduction band offset (∆EC) of ≈0.28 eV between a‐IZO and a‐IGZO layers and a conduction band bending of ≈0.3 eV at a‐IGZO/gate insulator (GI) interface exist. Through the electrical characterization, high field‐effect mobility (μFE) of ≈50 cm2 V−1 s−1, a positive threshold voltage (VTh) of ≈2.3 V, and low off‐current (IOFF) of <1 pA in coplanar a‐IZO/a‐IGZO TFT are demonstrated. The electron accumulation (>5 × 1018 cm−3) at both the a‐IZO/a‐IGZO and a‐IGZO/GI interfaces confirm the dual‐channel conduction. The bottom a‐IZO channel significantly contributes to increasing drain current (ID) due to large electron density (≈1019 cm−3). The dual‐channel coplanar TFT with a‐IGZO/IZO provides a guideline for overcoming the trade‐off between high μFE and positive VTh control for stable enhancement mode operation with increased ID.
We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of ∼350 nm and a protrusion height of ∼35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration (∼5 × 10 16 cm −3) at GB protrusion site was obtained as compared to the grain (∼3 × 10 18 cm −3). Trapping concentration at GB is much higher, which leads to the reduction in the mobility. INDEX TERMS Low temperature polycrystalline silicon (LTPS), thin-film transistors (TFTs), technology computer-aided design (TCAD).
Possible mechanisms to achieve high mobility in zinc oxynitride (ZnON) have been investigated by comparison with other thin film semiconductors. Integrated processes to fabricate ZnON TFTs have been developed. Issues and challenges encountered at current stage will be discussed.
Self‐aligned coplanar thin‐film transistors (TFTs) with a novel dual channel architecture comprising of low mobility and high mobility oxide semiconductors show high field‐effect mobility of > 50 cm2/Vs with positive threshold voltage of > 0 V and low off‐leakage current of < 1 pA. The TFTs with dual channel allow higher mobility than TFTs with a single high mobility channel because the TFTs with dual channel allow strong electron accumulation due to high electron densities both at the interface between gate insulator and 1st oxide semiconductor and at the hetero‐junction interface between 1st and 2nd oxide semiconductors.
Highly stable top-gate InGaZnO (IGZO) thin-film transistors (TFTs) with excellent threshold voltage (Vth) uniformity are developed by optimizing gate insulator film properties and controlling oxygen/hydrogen diffusion into IGZO channel. The TFTs do not show notable negative Vth shift and Vth nonuniformity from channel length 10 µm down to 3 µm.
Author KeywordsTop-gate TFTs; indium gallium zinc oxide (IGZO); short channel length; oxygen vacancy, hydrogen diffusion, PBTS, NBTS
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