No abstract

An amorphous indium gallium zinc oxide (a‐IGZO) layer is deposited on very thin conductive amorphous indium zinc oxide (a‐IZO) thin film to demonstrate high‐performance, coplanar thin‐film transistors (TFTs) with dual‐channel oxide semiconductor architecture. Based on material properties, a conduction band offset (∆EC) of ≈0.28 eV between a‐IZO and a‐IGZO layers and a conduction band bending of ≈0.3 eV at a‐IGZO/gate insulator (GI) interface exist. Through the electrical characterization, high field‐effect mobility (μFE) of ≈50 cm2 V−1 s−1, a positive threshold voltage (VTh) of ≈2.3 V, and low off‐current (IOFF) of <1 pA in coplanar a‐IZO/a‐IGZO TFT are demonstrated. The electron accumulation (>5 × 1018 cm−3) at both the a‐IZO/a‐IGZO and a‐IGZO/GI interfaces confirm the dual‐channel conduction. The bottom a‐IZO channel significantly contributes to increasing drain current (ID) due to large electron density (≈1019 cm−3). The dual‐channel coplanar TFT with a‐IGZO/IZO provides a guideline for overcoming the trade‐off between high μFE and positive VTh control for stable enhancement mode operation with increased ID.

Indium gallium zinc oxide is an amorphous oxide semiconductor (AOS) which has been regarded as a substitute for hydrogenated amorphous silicon. Other AOSs have been investigated but have needed multiple cations to reach high mobilities. Nonetheless, amorphous tin oxide (a-SnOx) has demonstrated thin-film transistors (TFTs) with high mobility. Here, we analyze the impact of the interface between the HfO2 dielectric and the tin oxide active layer on the performances of the TFTs. By analysis of electrical (through TFT devices) and chemical (through X-ray photoelectron spectroscopy measurements) properties and using technology computer-aided design, we can understand the origin of the high field-effect mobility (>90 cm2/V s). From the low contact and channel resistances and the large carrier concentration (∼1019 cm–3) to the large conduction band offset (2.59 eV) and the low exponentially distributed conduction band tail state (N TA) of 2.3 × 1019 cm–3 eV–1, the origin of the high performance has been investigated in depth.

We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of ∼350 nm and a protrusion height of ∼35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration (∼5 × 10 16 cm −3) at GB protrusion site was obtained as compared to the grain (∼3 × 10 18 cm −3). Trapping concentration at GB is much higher, which leads to the reduction in the mobility. INDEX TERMS Low temperature polycrystalline silicon (LTPS), thin-film transistors (TFTs), technology computer-aided design (TCAD).

The effect of electro‐thermal stress on the electrical performance of flexible, low‐temperature polysilicon (LTPS) thin‐film transistors (TFTs) after mechanical‐folding stress aiming to improve the reliability of foldable display backplanes is studied (IG). Herein, for the first time, the significant increase of gate leakage currents upon the negative bias temperature stress (NBTS) or positive bias temperature stress (PBTS) after the out‐folding test on excimer laser annealing (ELA) TFTs is reported. Out‐folding stress increases the drain current, shifts the threshold voltage (ΔVTH) by 2.4 V, and increases the subthreshold swing without affecting the (IG). However, the ΔVTH is 1.8 V upon NBTS, and the negative ΔVTH is −4.7 V upon PBTS after out‐folding stress along with a drastic increase in IG. A thermal annealing at 250 °C for 10 h for the electro‐thermal stressed TFTs after out‐folding is performed, and initial electrical characteristics recovery is achieved; except the abruptly increased IG. These results are correlated with charge trapping at the damaged grain boundary and (GI). A model with moisture/water molecule diffusion through the nanocracks generated by out‐folding is proposed. The ionized charges (H+, OH−) captured at the nanocrack‐induced trap sites in poly‐Si and GI appear to be the origin of abnormal ΔVTH and IG.