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As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single-and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

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Safe, high-rate and cost-effective cell sorting is important for clinical cell isolation. However, commercial fluorescence-activated cell sorters (FACS) are expensive and prone to aerosol-induced sample contamination. Here we report a microfluidic cell sorter allowing high rate and fully enclosed cell sorting. The sorter chip consists of an array of micro heating hotspots. Pulsed resistive heating in the hotspots produces numerous micro vapor bubbles with short duration, which gives rise to a rapid jet flow for cell sorting. With this method, we demonstrated high sorting rate comparable to commercial FACS and the significant enrichment of rare cancer cells. This vapor bubble based cell sorting method can be a powerful tool for contamination-free and affordable clinical cell sorting such as circulating tumor cell isolation and cancer cell therapy.

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