Through-silicon via and die stacking technologies for microsystems-integration

Beyne, Eric; Moor, Piet De; Ruythooren, Wouter; Labie, Riet; Jourdain, Anne; Tilmans, H.A.C.; Tezcan, Deniz Sabuncuoglu; Soussan, Philippe; Swinnen, Bart; Cartuyvels, R.

doi:10.1109/iedm.2008.4796734

Cited by 68 publications

(30 citation statements)

References 7 publications

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“…These TSVs achieve high integration density and may be fabricated with a high aspect ratio between values 5 and 25. For the second TSV scheme a via last approach is considered where the TSVs are fabricated after the wafers are thinned by processing the backside of the waferWafer level processing (3D-WLP) TSVs [17]. In this example the TSV diameter is 35 micrometers and the TSV pitch is 60 micrometers.…”

Section: Tsv Integration Densitymentioning

confidence: 99%

Impact of 3D design choices on manufacturing cost

Velenis

Stucchi

Marinissen

et al. 2009

2009 IEEE International Conference on 3D System Integration

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The available options in 3D IC design and manufacturing have different impact on the cost of a 3D Systemon-Chip. Using the 3D cost model developed at IMEC, the cost of different system integration options is analyzed and the cost effectiveness of different technology solutions is demonstrated. The cost model is based on the IMEC 3D integration process flows and includes the cost of manufacturing equipment, fabrication facilities, personnel, and materials. Using the IMEC 3D cost model, the cost of various 3D stacking strategies is compared to single die (i.e. 2D) integration. In addition, the effect on cost of different Through-Silicon-Via (TSV) manufacturing technologies is evaluated. The effectiveness of different 3D testing strategies and their impact on system cost is also investigated.

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Section: Tsv Integration Densitymentioning

confidence: 99%

Impact of 3D design choices on manufacturing cost

Velenis

Stucchi

Marinissen

et al. 2009

2009 IEEE International Conference on 3D System Integration

Self Cite

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“…There is also increased concern over mechanical reliability failure with filled Cu TSVs, due to the Cu-Si CTE mismatch. To limit TSV metallization thickness, while still having filled vias, others have demonstrated filling with dissimilar materials such as polymers [12], or used annular ring-shaped TSVs with Si cores in the center [5]. These methods can also have some challenges.…”

Section: Introductionmentioning

confidence: 98%

Fabrication of TSV-based silicon interposers

Malta

Vick

Goodwin

et al. 2010

2010 IEEE International 3D Systems Integration Conference (3DIC)

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Silicon interposers with through-silicon vias (TSVs) will enable further miniaturization and reduction in power consumption for future electronic systems. The design and method of integration of the TSVs can have a significant effect on the interposer process complexity, yield, and reliability. This paper will compare two different process approaches for Si interposer fabrication. In one approach, TSVs were formed "TSVs last", following the front-side multi-level metallization (MLM) processing, and were lined with copper, but were not filled. The second approach was a "TSVs first" process in which copper-filled TSVs were formed in silicon wafers prior to frontside MLM processing. These wafers were processed through front-side Cu CMP and back-side wafer thinning, leaving Cufilled TSVs exposed from both sides. The resulting TSV substrates could then be used for interposer fabrication involving front-side and back-side metal processing. This paper will summarize the fabrication and testing of TSV electrical test structures and interposer wafers using the TSVs-last process. For the TSVs-first process, which is still in development, the paper will review the demonstrations of key process modules and discuss integration and reliability considerations.

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“…3D through silicon vias (TSVs) integrated in advanced CMOS ICs [1], pose serious concerns about the influence of TSV-induced stress on devices nearby. For this reason, the diameter of TSVs is expected to shrink to reduce the TSV keep-out-zone [2][3][4].…”

Section: Introductionmentioning

confidence: 99%