Development of vertical and tapered via etch for 3D through wafer interconnect technology

Tezcan, Deniz Sabuncuoglu; Munck, Koen De; Pham, Nga; Lühn, Ole; Aarts, Arno; Moor, Piet De; Baert, Kris; Hoof, Chris Van

doi:10.1109/eptc.2006.342685

Cited by 31 publications

(34 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A 200-nm PVD Ti/Cu thin film has been deposited on the front-side as seed layer for the Cu sealing process. The bottom-up via dc electroplating have been carried out similar to techniques used by other groups [5], [6], [10], [12]. Prior to Cu plating, a plastic foil has been applied on the front-side to prevent the overgrowth of Cu and to enhance the sealing of vias.…”

Section: Wafer Layout and Fabrication Technologymentioning

confidence: 99%

See 1 more Smart Citation

RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration

Lamy

Jinesh

Roozeboom

et al. 2010

IEEE Trans. Adv. Packag.

View full text Add to dashboard Cite

show abstract

Section: Wafer Layout and Fabrication Technologymentioning

confidence: 99%

“…We mimic here a worse case scenario. The 20--diameter vias were etched in a STS DRIE etcher with inductively coupled plasma, using a typical Bosch etch process to 1521-3323/$26.00 © 2010 IEEE achieve vertical sidewalls [2], [12]. A 2.5-PECVD layer was used as hard mask.…”

Section: Wafer Layout and Fabrication Technologymentioning

confidence: 99%

RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration

Lamy

Jinesh

Roozeboom

et al. 2010

IEEE Trans. Adv. Packag.

View full text Add to dashboard Cite

show abstract

“…The etch rate of DRIE is aspect ratio dependent (ARDE) and may cause several topographic imperfections on the sidewalls such as scalloping, caused by alternating etchand passivation-steps, which results in corrugated sidewalls. By using state-of-the-art DRIE equipment, these effects can be minimized [12] and adopted to the demands of subsequent insulation, barrier and seed-layer deposition steps. Laser ablation is an emerging low-cost and high-speed process for drilling TSV holes as it benefits from the absence of any lithographic process steps and is agnostic to different materials.…”

Section: Introductionmentioning

confidence: 99%

“…Established processes are electrodeposition of copper [7,8,11,13,14,18], CVD of tungsten [2,19], CVD of polysilicon [2,12] and the use of low-resistivity silicon [10]. Especially electrodeposition of copper, being a very well-established semiconductor process, is used by many research groups and implemented in most commercialized devices containing TSVs.…”

Section: Introductionmentioning

confidence: 99%

“…Basic via designs are either based on solid or lined metallizations for the vertical conductor. TSVs can have either straight [7][8][9][10][11] or tapered sidewall profiles [12,13] as well as combinations of both [1,14]. Various methods for the formation of via holes exist and can be categorized into dry etching [1,7,8,[10][11][12][13][14], wet etching [14] and drilling processes [4].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Fischer

Bleiker

Somjit

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

View full text Add to dashboard Cite

Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (> 8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications. IntroductionDuring the past decades, hybrid integration of IC and MEMS technology has been dominated by 2-D approaches, resulting in Multi-Chip Modules (MCM) where different dies are integrated on a single substrate, and System-on-Chip (SoC) solutions where different functionalities are merged onto one die. CMOS and MEMS processing are both well-established and cost-efficient base technologies that are characterized by short development times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and their subsequent integration into a System-in-Package (SiP) offers high versatility and low process costs, and thus is an attractive alternative to SoC solutions. Especially 3D-integrated System in Package (3D-SiP) solutions, which are based on vertical chip stacking, are a general trend in many integration approaches. Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers. Large development efforts for the realization of reliable and cost-efficient TSVs are currently ongoing and the first commercially available devices such as MEMS inertial sensors and microphones, CMOS imagers and power LEDs successfully incorporate TSV technology [4][5][6].

show abstract

Deep Reactive Ion Etching of Through Silicon Vias

Roozeboom

Blauw

Lamy

et al. 2008

Handbook of 3D Integration

View full text Add to dashboard Cite

Development of vertical and tapered via etch for 3D through wafer interconnect technology

Cited by 31 publications

References 9 publications

RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration

RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

Deep Reactive Ion Etching of Through Silicon Vias

Contact Info

Product

Resources

About