This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ∼ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.
A complex switched capacitor sigma-delta ADC is described. The ADC is used in the VLIF RX path of a GSM/GPRS/EDGE phone and has an SNDR of 90dB in a 180kHz bandwidth, with the VLIF centered at 123kHz. The use of a complex noise transfer function allows for a more optimal use of noise shaping. The ADC is 2 nd order, 1-bit, with a sampling rate of 52MHz implemented in 90nm CMOS.
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