A Low-Power 1-V Supply Dynamic Comparator

Chevella, Subhash; O’Hare, Daniel; O’Connell, Ivan

doi:10.1109/lssc.2020.3009437

Cited by 48 publications

(19 citation statements)

References 7 publications

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“…In fact, to reduce the transition dynamic power, Mtail2 must be turned on after turning MR1 (MR2) off, which means that the terms in the above parenthesis at the right side of Equation (8), are approximately zero.…”

Section: R On3ð4þ C F Nðf Pþ Dt ð5þmentioning

confidence: 99%

“…In [1,[8][9][10][11][12][13][14] and [26][27][28], the positive feedback circuit has been added to the core body of the pre-amplifier stage to significantly reduce the comparator response time (delay). However, the positive feedback circuit itself increases both the power consumption as well as the input-referred noise [1].…”

mentioning

confidence: 99%

“…Many studies have been carried out to improve one or more of the abovementioned parameters or to provide different circuit techniques to improve the overall performance of the whole comparator circuit [5][6][7][8][9][10]. However, due to the disadvantages of the conventional dynamic comparators including: high delay, high dynamic power consumption and input-referred voltage errors; the designers have led to the development of the modified double-tail dynamic comparators [5].…”

mentioning

confidence: 99%

“…For example, in [1], two transistors are utilised in series with the input differential pair as control switches in the pre-amplifier stage, to control the power consumption of the circuit. However, a larger chip area, incapability to operate in low supply voltages, and high input-referred noise due to the use of positive feedback block in the pre-amplifier stage, are the major disadvantages of the designs reported in [1,[8][9][10][11][12][13][14]. On the other hand, realising the integrated circuits in the subthreshold region and bulk-drive techniques are the main two approaches that significantly reduce the power consumption, while increase in the delay of the circuit can be considered as a reduction in the speed performance.…”

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confidence: 99%

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An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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Section: R On3ð4þ C F Nðf Pþ Dt ð5þmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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“…The stimulating result shows the efficiency of the proposed comparator is seven times larger than the conventional Strong-Arm latch. Furthermore, S. Chevella presents a low voltage supply dynamic comparator in a 65 nm CMOS against a double tail latch comparator in 2020 [4]. The proposed comparator drops the power consumption by adding cross-coupled devices while keeping a similar noise level.…”

Section: Introductionmentioning

confidence: 99%

A Study on Design and Optimization methods in Latch Type Comparator

Chen

Zhi‐Jian

2022

J. Phys.: Conf. Ser.

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The current state-of-the-art communication systems require analog-to-digital converters (ADCs) to sample the analog signals in digital representation at high speed and low power consumption with very high accuracy. Performance demand for ADCs directly promote the advancement of their basic component - the comparator. The traditional Strong-Arm dynamic comparator has been widely accepted for its fast decision, but it is limited by its significant voltage headroom and kickback noise. The double-tail latched dynamic comparator mitigates the aforementioned problems by allowing separate stages for the pre-amplifier and the latch so that it can have near- operation. However, energy consumption and propagation delay are still problems to be solved. In this article, we present a review of the recent improvements for the dynamic comparator architecture. The advantages and disadvantages of these techniques are also illustrated with simulation and measurement results.

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