Abstract-We present Approximate BDD Minimization (ABM) as a problem that has application in approximate computing.Given a BDD representation of a multi-output Boolean function, ABM asks whether there exists another function that has a smaller BDD representation but meets a threshold w.r.t. an error metric. We present operators to derive approximated functions and present algorithms to exactly compute the error metrics directly on the BDD representation. An experimental evaluation demonstrates the applicability of the proposed approaches.
Abstract-Solvers for Boolean Satisfiability (SAT) are state-of-the-art to solve verification problems. But when arithmetic operations are considered, the verification performance degrades with increasing data-path width. Therefore, several approaches that handle a higher level of abstraction have been studied in the past. But the resulting solvers are still not robust enough to handle problems that mix word level structures with bit level descriptions.In this paper, we present the satisfiability solver SWORD -a SAT like solver that facilitates word level information. SWORD represents the problem in terms of modules that define operations over bit vectors. Thus, word level information and structural knowledge become available in the search process. The experimental results show that on our benchmarks SWORD is more robust than Boolean SAT, K*BMDs or SMT.
The open source library SystemC aids the composition of system level designs. The library offers a wide variety of datatypes and a simulation kernel. Both components help to describe VLSI designs very close to the RT level or at the more abstract system level. Since SystemC is based on C++, it allows the integration of several techniques into the model which do not contribute to the model itself, e.g. for verification, system exploration or debugging. But especially for debugging it is helpful to hide all these additional elements. This work addresses the problem of SystemC visualization for debugging backends. Besides displaying a system's behavior and its structure, our approach also excludes non-relevant data which is part of the system description, but does not define its behavior or its structure.
Today, the underlying hardware of embedded systems is often verified successfully. In this context formal verification techniques allow to prove the functional correctness. But in embedded system design the integration of software components becomes more and more important. In this paper we present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking. Besides correctness proofs of the underlying hardware the hardware/software interface and programs using this interface can be formally verified.
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