Checkers for systemC designs

Grobe, Daniel; Drechsler, Rolf

doi:10.1109/memcod.2004.1459851

Cited by 14 publications

(8 citation statements)

References 8 publications

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“…For example, Intel reported recently of its Fedex tool [1], which is used to monitor assertions written in the formal language ForSpec. There are no nontrivial technical barriers to incorporating assertion-based validation in SystemC dynamic validation [20]. This requires also integrating a BDD package into SystemC; see [12] for a report of such integration.…”

Section: Verification Of Systemc Designsmentioning

confidence: 99%

Formal techniques for SystemC verification

Vardi

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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SystemC has emerged lately as a de facto, open, industry standard modeling language, enabling a wide range of modeling levels, from RTL to system level. Its increasing acceptance is driven by the increasing complexity of designs, pushing designers to higher and higher levels of abstractions.While a major goal of SystemC is to enable verification at higher level of abstraction, enabling early exploration of system-level designs, the focus so far has been on traditional dynamic validation techniques. It is fair to see that the development of formal-verification techniques for SystemC models is at its infancy. In spite of intensive recent activity in the development of formal-verification techniques for software, extending such techniques to SystemC is a formidable challenge. The difficulty stems from both the object-oriented nature of SystemC, which is fundamental to its modeling philosophy, and its sophisticated event-driven simulation semantics.In this position paper we discuss what is needed to develop formal techniques for SystemC verification, augmenting dynamic validation techniques. By formal techniques we refer here to a range of techniques, including assertion-based dynamic validation, symbolic simulation, formal test generation, explicit-state model checking, and symbolic model checking.

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Section: Verification Of Systemc Designsmentioning

confidence: 99%

Formal techniques for SystemC verification

Vardi

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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“…In [17], a denotational semantics for the SystemC scheduler and for SystemC processes is presented, but only for a synchronous subset. Similarly, in [7,8] some work on formal verification of SystemC designs is done, but only for the synthesizable subset. In contrast to our approach, they are not able to cope with dynamic sensitivity or timing.…”

Section: Introductionmentioning

confidence: 99%

Model checking SystemC designs using timed automata

Herber

Fellmuth

Glesner

2008

Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of SystemC by a mapping from SystemC designs into the well-defined semantics of Uppaal timed automata. The informally defined behavior and the structure of SystemC designs are completely preserved in the generated Uppaal models. The resulting Uppaal models allow us to use the Uppaal model checker and the Uppaal tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice.

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“…So far, there is not one single technique that covers all demands [1] and for this, the verification tool CheckSyC [5,6] provides different verification approaches that include formal techniques and simulation approaches based on checkers. Simulation techniques are known to be "less powerful" regarding the completeness, but due to the complexity of the systems it happens that a formal proof fails.…”

Section: Figure 1 Overall Flow Of Sycementioning

confidence: 99%

“…The design environment consists of four main components: a parser (including logic synthesis options), a verification tool, a debugging tool, and a visualization component. The project started three years ago and in the meantime first results on the individual tools have been published in [7,5,4,3,6]. Here, for the first time the complete design environment is described and the latest features are highlighted.…”

Section: Introductionmentioning

confidence: 99%