Although a directed assembly strategy has been utilized for the massive assembly of various nanowires and nanotubes (NWs/NTs), its application has usually been limited to rather small-diameter NWs/NTs prepared in solution. We report two complementary methods for the massive assembly of large-size ZnO nanowires (NWs). In the solution-phase method, ZnO NWs were assembled and aligned selectively onto negatively charged surface patterns in solution. In addition, the substrate bias voltage and capillary forces can be used to further enhance the adsorption rate and degree of alignment of ZnO NWs, respectively. In the direct-transfer method, a NW film grown on a solid substrate was placed in close proximity to a molecule-patterned substrate, and ultrasonic vibration was applied so that the NWs were directly transferred and aligned onto the patterned substrate. The solution-phase and direct-transfer methods are complementary to each other and suitable for the assembly of NWs prepared in solution and on solid substrates, respectively.
Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.
Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.
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