Jitter Amplification Considerations for PCB Clock Channel Design

Abstract

Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

“…To validate this for the 4 backplane channels of Figure 5(a), the jitter impulse response [5,[10][11][12] is generated by extracting the channel output jitter pattern from a 5 GHz clock input with a 1 ps impulse applied to a rising edge. The channels' jitter transfer functions are obtained by performing a DFT on this output jitter pattern and are shown in Figure 5(b) plotted up to the clock frequency to capture duty cycle distortion (DCD) jitter.…”

System design considerations for a 5Gb/s source-synchronous link with common-mode clocking

“…In contrast, CM impedance is generally not well controlled as long as the CM voltage satisfies the receiver specification. In our application, even though reflections on the CM clock are less detrimental than reflections on data, reflections do introduce additional signal loss and jitter accumulation [4]. Moreover, in our target application, we would like to be able to turn on and off the chip interface as quickly as possible.…”

High-speed I/O jitter modeling methodologies

“…It has been shown that limited channel bandwidth results in jitter amplification [7,8]. In particular, high-frequency jitter directory modulates transmitted pulse width, therefore results in severe jitter amplification.…”

“…For clock channel, jitter amplification of the passive channel can be characterized by its jitter transfer function [7].…”

“…In contrast, some components may amplify jitter. For example, if the clock channel has insufficient bandwidth, it will amplify highfrequency jitter such as DCD and severely limit link performance [7,8]. Moreover, if the same jitter is present on both clock and data path, its impact on link margin might be reduced (jitter tracking) or amplified (jitter anti-tracking), depending on the jitter frequency and the timing skew between the data and clock path [9].…”