Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Kim, Joong-Ho; Kim, Woopoung; Oh, Dan; Schmitt, R.; Feng, June; Yuan, Chuck; Luo, Lei; Wilson, John

doi:10.1109/epep.2007.4387159

Cited by 23 publications

(13 citation statements)

References 4 publications

(4 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To examine the impact of SSO noise on the voltage and timing margin, the channel model shown in Fig. 9 was simulated with ideal and non-ideal power supply models [4]. Fig.…”

Section: Reducing Power Consumption Using Near Ground Signaling (mentioning

confidence: 99%

See 1 more Smart Citation

Challenges and solutions for next generation main memory systems

Kim

Kollipara

et al. 2009

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems

Self Cite

View full text Add to dashboard Cite

Today's high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view. I. CHALLENGES OF MAIN MEMORY SYSTEM DESIGNSDriven by recent multi-core computing, virtualization and processor integration trends, the data rate of a next generation main memory system for in high-end computer and workstation applications is expected to reach 3200Mb/s. In order to minimize system cost and provide backward compatibility, single-ended signaling based on Stub-Series Terminated Logic (SSTL) is the logic choice for next generation main memory I/O interfaces. Unfortunately, as the target data rate for memory interface continues to increase, signal integrity issues such as crosstalk, simultaneous switching output (SSO) noise, and reference voltage (VREF) noise, have become major limiting factors for potential data rates in high-speed memory interfaces [1].In addition to these conventional signal integrity issues, the main memory applications pose additional challenges due to the signal noise generated by multiple memory module loadings. In these multi-drop topologies, the major factor that determines the maximum speed of the memory bus is the worst-case loading characteristics in which all connectors are fully populated with memory modules. As a consequence, the number of modules that can be supported in a multi-drop architecture decreases with increasing bus speed. Fig. 1 shows the number of device drops per data pin versus data rate. As illustrated in this figure, the high data rate prohibits any multi-drops beyond 1333 or 1600Mb/s. This limitation has the effect of reducing the total system memory capacity. As such, alternative methods for achieving high capacity are desirable. This paper introduces three key technologies to enhance the current DDR3 technology to beyond 1600Mb/s [3]. The FlexPhase™ technology removes significant timing errors extending the potential data rate. The dynamic point-to-point technology enables multiple memory modules to be implemented as point-to-point signaling to increase the memory capacity. Finally, the near ground signaling technology reduces the total I/O interface power without sacrificing the signal quality. To demonstr...

show abstract

“…To examine the impact of SSO noise on the voltage and timing margin, the channel model shown in Fig. 9 was simulated with ideal and non-ideal power supply models [4]. Fig.…”

Section: Reducing Power Consumption Using Near Ground Signaling (mentioning

confidence: 99%

“…To predict the maximum channel performance, we used the optimized passive channel: the motherboard impedance is optimized with compensating filters in order to minimize ISI impact. We used a simulation methodology described in [4] to perform simulation including analysis SSO noise.…”

mentioning

confidence: 99%

Challenges and solutions for next generation main memory systems

Kim

Kollipara

et al. 2009

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…When the aggregate signaling current of a wide, parallel bus flows through the PDN of an electrical system, this current induces voltage fluctuations on the power supply [1]. These voltage fluctuations are the by-product of large signaling currents (e.g.…”

Section: Introductionmentioning

confidence: 99%

Equalization of mid-frequency power supply noise via a spectrum-shaping encoder for parallel buses

Wilson

Abbasfar

Ren

et al. 2009

2009 59th Electronic Components and Technology Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…In this section, an SI and PI co-simulation methodology presented in [4,5] is briefly reviewed using an x32 graphic memory system (GDDR) as a demonstration vehicle. Fig.…”

Section: Introductionmentioning

confidence: 99%

A study of reduced-terminal models for system-level SSO noise analysis

Kim

et al. 2010

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

Self Cite

View full text Add to dashboard Cite

SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options to reduce the number of external nodes for SSO simulation. Both signal and power nodes are reduced based on the worst case aggressor switching activities. Significance of placing supernode in reduction of signal nodes is discussed. Low power memory system is considered as a numerical example to demonstrate and compare the accuracy of each option.

show abstract

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Cited by 23 publications

References 4 publications

Challenges and solutions for next generation main memory systems

Challenges and solutions for next generation main memory systems

Equalization of mid-frequency power supply noise via a spectrum-shaping encoder for parallel buses

A study of reduced-terminal models for system-level SSO noise analysis

Contact Info

Product

Resources

About