Precursor ISI Reduction in High-Speed I/O

Ren, Jihong; Lee, Haechang; Lin, Qilang; Leibowitz, Brian; Chen, E-Hung; Oh, Dan; Lambrecht, F.; Stojanović, Vladimir; Yang, Chih-Kong Ken; Zerbe, J.

doi:10.1109/vlsic.2007.4342687

Cited by 20 publications

(15 citation statements)

References 3 publications

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“…In such pre-emphasis schemes, delayed copies of the symbols are weighted and summed to create equalizing finite impulse response (FIR) filters [97,98,[111][112][113][114][115][116][117].…”

Section: Transmitter-side Equalizationmentioning

confidence: 99%

“…Most transceivers that use discrete-time equalization at the receiver, combine equalization with variants of LMS algorithms to adapt the coefficients, most often so-called signedsigned LMS [106,111,[113][114][115]145]. Sometimes, the LMS algorithm is slightly modified to also minimize ISI at the left and right edge of the eye [119] and thereby reduce the datadependent jitter, or it can contain additives such as an eye opening monitor [138].…”

Section: Adaptive Equalizationmentioning

confidence: 99%

“…The adaptation algorithms are sometimes used primarily for the receiver (DFE) equalizer [113][114][115]119], or in other implementations, there is return communication to also adapt the transmitter side equalizer [106,111,135,136]. Often, a mix of startup calibration with a training sequence and online adaptation is used, especially when the transmitter is also adaptive.…”

Section: Adaptive Equalizationmentioning

confidence: 99%

“…Some receivers with loop-unrolled DFE manage to do this by using more complex phase detectors than the classical Hogge or Alexander detectors, using for example multiple edge detectors with different thresholds (an 'unrolled' edge detector) [115] or an 'eye tracking' phase-detector that does not sample on the edge but just before and after it [116].…”

Section: Adaptive Equalization and Clock Recoverymentioning

confidence: 99%

“…A method to avoid interference between the CDR and DFE control loops can be to either use very different convergence speeds for the two loops [112] or to combine the two into a single control algorithm [113,115,136]. A simple method to combine CDR with adaptive receiver equalization is for example presented in [113].…”

Section: Adaptive Equalization and Clock Recoverymentioning

confidence: 99%

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On-chip data communication : analysis, optimization and circuit design

Schinkel¹

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“…In such pre-emphasis schemes, delayed copies of the symbols are weighted and summed to create equalizing finite impulse response (FIR) filters [97,98,[111][112][113][114][115][116][117].…”

Section: Transmitter-side Equalizationmentioning

confidence: 99%

Section: Adaptive Equalizationmentioning

confidence: 99%

Section: Adaptive Equalizationmentioning

confidence: 99%

Section: Adaptive Equalization and Clock Recoverymentioning

confidence: 99%

Section: Adaptive Equalization and Clock Recoverymentioning

confidence: 99%

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On-chip data communication : analysis, optimization and circuit design

Schinkel¹

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Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

Yuan

Al-Taee

et al. 2014

IET Circuits, Devices & Systems

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This study provides a comprehensive review of decision feedback equalisation (DFE) for multi-giga-bit-per-second (Gbps) data links. The state-of-the-art of DFE for multi-Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross-talk and their impact on data transmission are investigated. The fundamentals of both near-end and far-end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi-Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.

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A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

Wang

Chen

Liang

et al. 2009

2009 Canadian Conference on Electrical and Computer Engineering

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This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane environment, for high-speed, highly lossy band-limited channel, the pre-cursor inter-symbol interference (ISI) is still a significant problem for channel equalization. A programmable pre-cursor ISI equalizer combined with a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of -20 dB. The results show it outperform a traditional 5-tap DFE.

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Precursor ISI Reduction in High-Speed I/O

Cited by 20 publications

References 3 publications

On-chip data communication : analysis, optimization and circuit design

On-chip data communication : analysis, optimization and circuit design

Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

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