Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out.Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement.Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps).Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs.Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer.

The High Luminosity phase of the Large Hadron Collider will deliver 10 times more integrated luminosity than the existing collider, posing significant challenges for radiation tolerance and event pileup on detectors, especially for forward calorimetry. As part of its upgrade program, the Compact Muon Solenoid collaboration is designing a high-granularity calorimeter (HGCAL) to replace the existing endcap calorimeters. It will feature unprecedented transverse and longitudinal readout and triggering segmentation for both electromagnetic and hadronic sections. The electromagnetic section and a large fraction of the hadronic section will be based on hexagonal silicon sensors of 0.5–1 cm2 cell size, with the remainder of the hadronic section being based on highly-segmented scintillators with silicon photomultiplier readout. The intrinsic high-precision timing capabilities of the silicon sensors will add an extra dimension to event reconstruction, especially in terms of pileup rejection. First hexagonal silicon modules, using the existing Skiroc2 front-end ASIC developed for CALICE, have been tested in beams at Fermilab and CERN in 2016. We present results from these tests, in terms of system stability, calibration with minimum-ionizing particles and resolution (energy, position and timing) for electrons, and the comparisons of these quantities with GEANT4-based simulation.

A: SKIROC2_CMS is a chip derived from CALICE SKIROC2 that provides 64 channels of low noise charge preamplifiers optimized for 50 pF pin diodes and 10 pC dynamic range. They are followed by high gain and low gain 25 ns shapers, a 13-deep 40 MHz analog memory used as a waveform sampler at 40 MHz. and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA techniques at system level and in test-beam.The chip was sent to fabrication in January 2016 in AMS SiGe 0,35 µm and was received in May. It was tested in the lab during the summer and will be mounted on sensors for beam-tests in the fall.

As part of its HL-LHC upgrade program, the CMS Collaboration is developing a High Granularity Calorimeter (CE) to replace the existing endcap calorimeters. The CE is a sampling calorimeter with unprecedented transverse and longitudinal readout for both electromagnetic (CE-E) and hadronic (CE-H) compartments. The calorimeter will be built with ∼30,000 hexagonal silicon modules. Prototype modules have been constructed with 6-inch hexagonal silicon sensors with cell areas of 1.1 cm 2 , and the SKIROC2-CMS readout ASIC. Beam tests of different sampling configurations were conducted with the prototype modules at DESY and CERN in 2017 and 2018. This paper describes the construction and commissioning of the CE calorimeter prototype, the silicon modules used in the construction, their basic performance, and the methods used for their calibration.

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS m SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented. Index Terms-BiCMOS integrated circuits, mixed analog digital integrated circuits, photodetectors, positron emission tomography.

Concomitant with this increase will be an increase in the number of interactions in each bunch crossing and a significant increase in the total ionising dose and fluence. One part of this upgrade is the replacement of the current endcap calorimeters with a high granularity sampling calorimeter equipped with silicon sensors, designed to manage the high collision rates [2]. As part of the development of this calorimeter, a series of beam tests have been conducted with different sampling configurations using prototype segmented silicon detectors. In the most recent of these tests, conducted in late 2018 at the CERN SPS, the performance of a prototype calorimeter equipped with ≈12, 000 channels of silicon sensors was studied with beams of high-energy electrons, pions and muons. This paper describes the custom-built scalable data acquisition system that was built with readily available FPGA mezzanines and low-cost Raspberry PI computers.

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The High Granularity Calorimeter (HGCAL), presently being designed by the Compact Muon Solenoid collaboration (CMS) to replace the existing endcap calorimeters for the High Luminosity phase of the LHC, will feature unprecedented transverse and longitudinal readout and triggering segmentation for both electromagnetic and hadronic sections. The requirements for the front-end electronics are extremely challenging, including high dynamic range (0-10 pC), low noise (2000 electrons), highprecision timing information in order to mitigate the pileup effect (25 ps binning) and low power consumption (15 mW/channel). The front-end electronics will face a harsh radiation environment which will reach 200 Mrad at the end of life. It will work at a controlled temperature of 240 K. HGCROV-V2 is the second prototype of the front-end ASIC. It has 72 channels of the full analog chain: low noise and high gain preamplifier and shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge measurement over the linear range of the preamplifier. In the saturation range of the preamplifier, a discriminator and TDC provide the charge information from TOT (Time Over Threshold) over 200 ns dynamic range using 50 ps binning. A fast discriminator and TDC provide timing information to 25 ps accuracy. Both charge and timing information are kept in a DRAM memory waiting for a Level 1-trigger decision (L1A). At a bunch crossing rate of 40 MHz, compressed charge data are sent out to participate in the generation of the L1-trigger primitives. We report on the performances of the chip in terms of signal-to-noise ratio, charge and timing, as well as results from radiation qualification with total ionizing dose (TID).