The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging. Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer. As a drawback, an off-chip component and an additional LNA are introduced, raising costs.Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 0.18-m CMOS solution with outstanding linearity and noise performances. The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out. Sixty samples from two distinct fabrication lots have been characterized. Minimum IIP2 is +78 dBm. For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested. IIP2 values are always lower.Other measured performance results are: 16-dB gain with 4.5-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nVHz input referred noise voltage density while drawing 4 mA from 1.8 V.

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A 1.5 to 10Gb/s SATA/SAS/FC receiver in 65nm CMOS is presented. It is based on an adaptive 3-tap latch-based DFE data recovery with self-aligning capability and on an early-late digital clock recovery capable of SSC tracking. Extensive digital features allow self-calibration and eye analysis. The macro measures 0.3mm 2 and consumes 140mA from 1V at 8.5Gb/s. IntroductionThere is a growing interest toward multi-standard single chip transceivers for backplane interconnects in Hard Disk Drives. A solution addressing 1.5-3-6Gb/s SATA/SAS and 2.125-4.25-8.5Gb/s Fiber Channel (FC) would serve emerging data storage applications, but the different standards entail totally different requirements: the clock and data recovery (CDR) for 6Gb/s application has to be capable of spread spectrum clock (SSC) tracking, while in 8.5Gb/s FC the main challenges are data equalization and serial to parallel latency.VCO based analog CDRs have been proven for SSC tracking [1] but digital interpolator-based CDRs, by allowing VCO sharing, are attractive to save power and reduce VCO pulling risk. On the other hand, the intrinsic loop latency of digital CDRs has mainly limited their application to constant or moderate frequency shifts (<1000 ppm) [2]. Attempts to extend operation to 5000ppm have been made by means of SSC profile estimation [3], however limited to triangular profile. In addition to SSC, a multi-standard CDR has to withstand bandwidth variation caused by multi-rate operation and by data patterns with alternate sequences of low frequency and high frequency content (e.g. CJTPAT).Decision feedback equalization (DFE) has been widely applied to backplanes. Half-rate DFE [4] and loop unrolling [5], [6] have been proposed to overcome the DFE first tap speed requirements. These techniques, splitting the data between different paths, prevent exploitation of a conventional CDR, because of the lack of an equalized eye within a single identified transition region. Only partial solutions to this issue have been proposed and they lead to an increased hardware complexity. In [5], the CDR samplers are split between the two data paths, but the CDR edges analysis is limited to a subset of data sequences. This can prevent correct operation with data patterns not including these sequences. On the other hand, an independent non-DFE path for CDR as in [6] results in loosing the self-alignment to the recovered eye, because of the intrinsic eye shift caused the DFE. Leaving uncompensated this shift leads to jitter tolerance penalties.The aim of this work is to demonstrate the first architecture, to author's knowledge, fulfilling all the requirements of SATA/SAS/FC standards. A full-rate DFE has been implemented from half-rate clocking by means of a novel latch-based architecture capable of first tap delay minimization. Exploiting the reconstructed full-rate eye, a digital self-aligned CDR has been implemented. Custom techniques both in CDR digital domain and in demultiplexing have been developed to allow multi-rate operation and SSC tracking without th...

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