A CMOS direct down-converter with +78dBm minimum IIP2 for 3G cell-phones

Brandolini, M.; Rossi, Paolo; Sanzogni, D.; Svelto, F.

doi:10.1109/isscc.2005.1493998

Cited by 24 publications

(17 citation statements)

References 2 publications

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“…The problem of IM2 components generated in the transcondouctor is addressed in this design by gm-degeneration technique [6] in which the input transconductance is reduced in IF frequencies comparing to RF frequencies.…”

Section: The Proposed Mixermentioning

confidence: 99%

“…Regardless of complex calibration techniques [4,5], in the extent of our knowledge, the solution presented for this problem in CMOS technology is using a LC filter for tuning C P capacitor in LO frequency [6]. In this way IIP2 improvement by Q dB can be achieved in which Q is the inductor quality factor.…”

Section: Introductionmentioning

confidence: 99%

“…For using this LC filtering in multi-standard applications, a bank of inductors for reconfiguring the mixer in each band is needed. As the main drawback, the IIP2 improvement is highly decreased due to the degradation of Q in switched inductors [6]. This problem is addressed in this paper by a new reconfigurable inductor controlled by mutual current.…”

Section: Introductionmentioning

confidence: 99%

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A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

Vahidfar

Shoaei

2007

IEICE Electron. Express

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Abstract:A new technique for addressing the challenging dynamic range required by CMOS multi-standard Zero-IF GSM and UMTS receivers is presented in this paper. This is achieved by LC tuning of the parasitic capacitors of mixer switching transistors in different frequency bands with an easily reconfigured new integrated variable inductor. Using this technique, a high IIP2 low noise mixer supporting DCS, PCS, UMTS and IEEE802.11 b-g standards is designed. The mixer achieves IIP2 higher than 70 dBm while the input refereed noise performance is 5 and 3.5 nv/sqrt(Hz) in DCS/PCS and UMTS respectively. The design is done in 65 nm CMOS technology.

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Section: The Proposed Mixermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

Vahidfar

Shoaei

2007

IEICE Electron. Express

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“…On the other hand, several analog techniques, at RF in particular, have emerged in the recent past, improving both linearity and noise performances of different building blocks, due to an in-depth understanding of the underlying physical processes [2,3]. In this paper, a direct-conversion fully integrated RF front-end is proposed for GSM.…”

mentioning

confidence: 99%

“…The switching pair, set with the L 1 -C 1 filter, is highly linear [2]. Despite the effectiveness of the filter reducing the 1/f noise contribution, the GSM baseband signal spectrum occupies only 100kHz, requiring a comparatively low noise corner which is extremely challenging in a sub-micron CMOS implementation.…”

mentioning

confidence: 99%

A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS

Brandolini

Sosio

Svelto

2006

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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The dynamic range, required by wireless cell-phone terminals, makes the design of analog circuits at the supply voltage available in deep submicron CMOS technologies so challenging that researchers are investigating alternative methods to process the received signal [1]. On the other hand, several analog techniques, at RF in particular, have emerged in the recent past, improving both linearity and noise performances of different building blocks, due to an in-depth understanding of the underlying physical processes [2,3]. In this paper, a direct-conversion fully integrated RF front-end is proposed for GSM. Realized in 90nm CMOS, the chip operates at a supply voltage compatible with the 45nm node and demonstrates the following main performances: 3.5dB NF integrated between 1kHz and 100kHz, 15kHz 1/f noise corner, 51dBm minimum IIP2, at a supply voltage as low as 750mV. No calibration is required to meet the IIP2 specification.GSM is particularly demanding due to closely spaced channels and huge interferers surrounding the received signal. The resulting required 1/f noise corner and IIP2 usually suggests disregarding a direct-conversion architecture when the technology is CMOS, despite its attractiveness to arrive at a highly integrated transceiver implementation. The RF front-end can not rely on any frequency selectivity, having the most dangerous interferers only few MHz away from the received signal. As pointed out in Fig. 26.1.1, the down-converter is the most critical block where low 1/f noise and high linearity are conflicting requirements, at given current consumption [3,4]. Furthermore, the reduction in the available supply voltage of scaled processes calls for minimum device stacking, making a conventional Gilbert cell not attractive. In particular, a fully differential transconductor, though showing excellent IIP2 performances, determines a significant voltage drop to accommodate the biasing current source. The pseudo-differential alternative has the advantage of a lower voltage drop and a superior IIP3, though at the expense of a dramatically reduced IIP2. The second-order common-mode conductance gain is at the origin of much higher second-order inter-modulation products in the mixer output current [4]. The idea proposed in this paper is to minimize the inter-modulation current produced by a pseudo-differential transconductor by means of a feedback loop controlling the mixer output common-mode voltage. Referring to Fig. 26.1.2, where the mixer schematic is drawn, an opamp senses the difference between the common-mode output voltage and a reference and drives the PMOS device, P CM , supplying the common-mode current to the input transconductor. By inspection, the loop gain (G loop ) is given by:(1) where A is the opamp gain, g m,PCM is the tranconductance of P CM , and r ds,PL the output resistance of P L .The loop operates at a low frequency and can produce a large gain at minimum consumption, significantly reducing the commonmode inter-modulation current injected into the switching pair. To gain quantita...

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An IIP2 Calibration Technique for Zero-IF Multi Band down Converter Mixer

Vahidfar

Shoaei

2008

IEICE Transactions on Fundamentals of Electronics, Communicatio

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A CMOS direct down-converter with +78dBm minimum IIP2 for 3G cell-phones

Cited by 24 publications

References 2 publications

A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS

An IIP2 Calibration Technique for Zero-IF Multi Band down Converter Mixer

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