A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…Alternatively, the opening of data eyes can be used to guide DFE search [71,72]. Eye-opening can be captured using an Eye-Opening Monitor (EOM) [73][74][75][76][77][78][79][80][81]. Jitter-based eye-opening monitors that minimize timing jitter at the edges of data eyes also emerged [82].…”

On-chip data communication : analysis, optimization and circuit design

“…But DFE with more than a few taps tends to become complex and power hungry, so it is sometimes combined with a linear equalizer [111,112,116,137,138]. An often stated motivation is that linear equalizers can cancel long tails in the symbol response with lower complexity.…”

“…Sometimes, the LMS algorithm is slightly modified to also minimize ISI at the left and right edge of the eye [119] and thereby reduce the datadependent jitter, or it can contain additives such as an eye opening monitor [138]. Other adaptation algorithms have also been proposed, for example adaptations based on BER optimization [136,146].…”

“…This is especially so when loop-unrolling (see section 7.6) is used, because then there is no single stable transition point for a phase-detector to use, as discussed in [116,138]. So for many receivers with loop-unrolled DFE, the CDR is a standalone circuit that primarily uses the input signal to the DFE for phase detection [100,111,114], possibly also taking some information from the DFE output into account [135,141].…”

“…For the receivers that do not use loop-unrolled DFE, the CDR can be placed after the DFE with more ease [113,119,136,138]. But still, care has to be taken, as the recovered clock itself is used in the DFE, which creates an additional feedback loop that can interfere with the control algorithms.…”