VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subcircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here.

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Estimating the impact of Single Event Effects (SEEs) on SRAM-based FPGA devices is a major issue in order to adopt them in radiation environments such as space or high altitude. Among the available approaches, we proposed an analytical method to predict SEE effects based on the analysis of the circuit the FPGA implements, which does not require either simulation or fault injection. In this paper we provide an experimental validation of this approach, by comparing the results it provides with those coming from accelerated testing. We adopted our analytical method for computing the error cross section of a design implemented on SRAM-based FPGA devices. We then compared the obtained figure with that obtained by accelerated testing. Experimental analysis demonstrated that accelerated testing closely match the figures the analytical method provides.

Flash-based FPGAs are more and more interesting for space applications because of their robustness against Single Event Upsets (SEUs) in configuration memory. However, as Single Event Effects (SEEs) are still a concern both for user memory and the configurable logic, accurate evaluations are needed to identify mitigation techniques for securing their use in space missions. In this paper the SEE sensitivity of circuits implemented in Flash-based FPGAs is evaluated with respect to the working frequency and different routing schemes. We outline different methodologies that can be used in order to characterize SEE sensitivity, using both heavy-ions radiation experiments and analytical approaches. Experimental results detail the contributions of different SEEs as a function of operating frequency and routing on a realistic circuit

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