Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-Based FPGAs

Abstract

Estimating the impact of Single Event Effects (SEEs) on SRAM-based FPGA devices is a major issue in order to adopt them in radiation environments such as space or high altitude. Among the available approaches, we proposed an analytical method to predict SEE effects based on the analysis of the circuit the FPGA implements, which does not require either simulation or fault injection. In this paper we provide an experimental validation of this approach, by comparing the results it provides with those coming from accelerated testing. We adopted our analytical method for computing the error cross section of a design implemented on SRAM-based FPGA devices. We then compared the obtained figure with that obtained by accelerated testing. Experimental analysis demonstrated that accelerated testing closely match the figures the analytical method provides.

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

“…STAR [16] performs a low level analysis of the TMR-hardened circuit netlist, by building an internal representation which derives the various replicas' domains and the voters. By emulating the injection of single bit flips in each one of the used bits of the bitstream, the algorithm identifies those faults that have an effect in more than a single replica domain, thus invalidating the voting strategy.…”

Analysis and optimization of fault-tolerant embedded systems with hardened processors

“…We consider that the worst-case size of messages is given, which implicitly can be translated into the worst-case transmission time on the bus. In this paper we assume that communications are fault tolerant (i.e., we use a communication protocol such as TTP [10] [2], while process failure probabilities (p) are determined using fault injection tools [1,18].…”

“…Given is also a set of available computation nodes each with its available hardened h-versions and the corresponding costs. We know the worst-case execution times, and the failure probabilities are obtained with fault injection experiments [1,18] for each process on each h-version of computation node. The maximum transmission time of all messages, if sent over the bus, is given.…”

“…The process failure probability p ijh of process P i , executed on computation node N j with hardening level h, is obtained with simulation using fault injection tools such as [1,18]. Mapping of a process P i on the h-version of computation node N j will be denoted as M(P i ) = N j h .…”

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

“…The purpose of this paper is to present an experimental evaluation performed using fault injection campaigns of the approach we proposed in [9] and [12] to predict the circuit error-rate of designs implemented on SRAM-based FPGAs. As a result of the fault injection campaign we observed that the calculation we made closely matches the experimental results, indicating that the approach we propose can be an accurate and efficient estimation tool for the impact of SEUs in SRAM-based FPGAs.…”