Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

Desogus, Marco; Sterpone, Luca; Codinachs, David Merodio

doi:10.1109/iolts.2014.6873681

Cited by 17 publications

(5 citation statements)

References 8 publications

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“…These applications are implemented on Static Random Access Memory (SRAM)-based FPGA. SRAM FPGA devices are very critical to radiations and this may cause Single Event Effects (SEE) [5], [8], [9]. SEE is the combination of Single Event Transient (SET) and Single Event Upset (SEU).…”

Section: Introductionmentioning

confidence: 99%

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

Khatri¹

2020

IJACSA

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The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Faulttolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

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Section: Introductionmentioning

confidence: 99%

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

Khatri¹

2020

IJACSA

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“…The method consists of intentionally injecting faults into the device under test and observing the behaviour of faults/errors [1], [4]. Fault injection covers many fundamentals objectives: 1) Validate the design under test concerning reliability.…”

Section: Introductionmentioning

confidence: 99%

A Technical Guide for the RASP-FIT Tool

Khatri¹

2019

IJACSA

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Fault injection tools are designed to serve various purposes, such as validate the design under test concerning reliability requirements, find sensitive/critical locations that require error mitigation, determine the expected circuit response in the existence of faults. Fault Simulation/Emulation (S/E) applications are involved in Field Programmable Gate Array (FPGA) based design's verification and simulation at the Hardware Description Languages (HDL) code level. A tool is developed, named RASP-FIT, to perform code modification of FPGA designs, testing of such designs, and finding the sensitive area of designs. This tool works on the FPGA designs written in Verilog HDL at various abstraction levels, gate, data-flow and behavioural levels. This paper presents a technical aspect and the user-guide for the proposed tool in detail, which includes generation of the standalone application (an executable file of the tool for Windows operating system) and installation method.

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“…Therefore, FPGA has become the core of many embedded applications. SRAM-based FPGA devices are sensitive to Single Event Effects (SEE), which can be caused by various sources, such as α-particles, cosmic rays, atmospheric neutrons, heavy-ion radiations and electromagnetic radiations (x-rays or gamma rays) [2], [3], [4]. When a charged particle hits a critical node of FPGA-based design, it generates the transient pulse which can produce a bit-flip effect.…”

Section: Introductionmentioning

confidence: 99%

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

Khatri¹,

Hayek²,

̈ok³

2018

ijacsa

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Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system's complexity makes the reliability evaluation extremely difficult and costly. Redundancy techniques are widely used to increase the reliability of such systems. These techniques provide a large area & time overheads which cause more power consumption and delay, respectively. An experimental evaluation method is proposed to find critical nodes of the FPGA-based designs, named "hardness analysis technique" under the proposed RASP-FIT tool. After finding the critical nodes, the proposed redundant model is applied to those locations of the design and the code is modified. The modified code is functionally equivalent and is more hardened to the soft-errors. An experimental setup is developed to verify and validate the criticality of these locations found by using hardness analysis. After applying redundancy to those locations, the reliability is evaluated concerning failure rate reduction. Experimental results on ISCAS'85 combinational benchmarks show that a min-max range of failure reduction (14%-85%) is achieved compared to the circuit without redundancy under the same faulty conditions, which improves reliability.

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Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

Cited by 17 publications

References 8 publications

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

A Technical Guide for the RASP-FIT Tool

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

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