Analysis and optimization of fault-tolerant embedded systems with hardened processors

Izosimov, Viacheslav; Polian, Ilia; Pop, Paul; Eles, Petru; Peng, Zebo

doi:10.1109/date.2009.5090752

Cited by 35 publications

(31 citation statements)

References 24 publications

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“…Data representations, however, have been widely ignored. Radiation hardening is another common technique in fault protection for real-time systems [33], [34] with overheads in costs and speed. In contrast to our work, these solutions either promote hardware approaches or do not consider massive multi-cores (or even real-time systems).…”

Section: Resultsmentioning

confidence: 99%

Fault Resilient Real-Time Design for NoC Architectures

Zimmer

Mueller

2012

2012 IEEE/ACM Third International Conference on Cyber-Physical Systems

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Abstract-Performance and time to market requirements cause many real-time designers to consider components, off the shelf (COTS) for real-time cyber-physical systems. Massive multi-core embedded processors with network-on-chip (NoC) designs to facilitate core-to-core communication are becoming common in COTS. These architectures benefit real-time scheduling, but they also pose predictability challenges. In this work, we develop a framework for Fault Observant and Correcting Real-Time Embedded design (Forte) that utilizes massive multi-core NoC designs to reduce overhead by up to an order of magnitude and to lower jitter in systems via utilizing message passing instead of shared memory as the means for intra-processor communication. Message passing, which is shown to improve the overall scalability of the system, is utilized as the basis for replication and task rejuvenation. This improves fault resilience by orders of magnitude. To our knowledge, this work is the first to systematically map real-time tasks onto massive multi-core processors with support for fault tolerance that considers NoC effects on scalability on an real hardware platform and not just in simulation.

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Section: Resultsmentioning

confidence: 99%

Fault Resilient Real-Time Design for NoC Architectures

Zimmer

Mueller

2012

2012 IEEE/ACM Third International Conference on Cyber-Physical Systems

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“…These approaches aim to increase the reliability of the system by checkpointing and dynamic voltage scaling [21], improved scheduling techniques, cf. [10,22], reliability-aware selection of components [11], or introducing redundancy at componentlevel [13,17,20], or process-level [5,6,8]. However, one can observe that nearly all reliability-increasing techniques result in an increase of cost in one or even several objectives like runtime, monetary costs, area consumption, or power consumption.…”

Section: Related Workmentioning

confidence: 99%

Towards scalable system-level reliability analysis

Glas

Lukasiewycz

Haubelt

et al. 2010

Proceedings of the 47th Design Automation Conference

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State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems:(1) The BDDs exhaust available memory during their construction and/or (2) the final size of the BDDs is, sometimes up to several orders of magnitude, larger than the available memory. The contribution of this paper is twofold: (1) A partitioning-based early quantification technique is presented that aims to keep the size of the BDDs during construction at minimum. (2) A SAT-assisted simulation approach aims to deliver approximated results when exact analysis techniques fail because the final BDDs exhaust available memory. The ability of both methods to accurately analyze larger and more complex systems than known approaches is demonstrated for various test cases.

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“…Instead of modeling faults as probabilistic events, they assume that the system may experience at most N faults and those faults may occur in any component of the system. In the follow-up work [7], a more accurate probabilistic analysis is presented. Nevertheless, this analysis considered only temporal redundancy.…”

Section: Appendix a Related Workmentioning

confidence: 99%

Towards fault-tolerant embedded systems with imperfect fault detection

Huang

Raabe

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a detailed experimental analysis, we observe that perfect fault detection is not only an impractical assumption but even if implementable also a suboptimal design decision. This paper presents an approach that takes imperfect fault detection into account. Novel analysis and optimization techniques are developed, which distinguish detectable and undetectable faults in the overall workflow. Besides synthesizing the task schedules, our approach also decides which of the available fault detectors is selected for each task instance. Experimental results show that our approach finds solutions with several orders of magnitude higher reliability than current approaches.

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Analysis and optimization of fault-tolerant embedded systems with hardened processors

Cited by 35 publications

References 24 publications

Fault Resilient Real-Time Design for NoC Architectures

Fault Resilient Real-Time Design for NoC Architectures

Towards scalable system-level reliability analysis

Towards fault-tolerant embedded systems with imperfect fault detection

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