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The development of laser-assisted atom-probe tomography (APT) analysis and new sample preparation approaches have led to significant advances in the characterization of semiconductor materials and device structures by APT. The high chemical sensitivity and three-dimensional spatial resolution of APT makes it uniquely capable of addressing challenges resulting from the continued shrinking of semiconductor device dimensions, the integration of new materials and interfaces, and the optimization of evolving fabrication processes. Particularly pressing concerns include the variability in device performance due to discrete impurity atom distributions, the phase and interface stability in contacts and gate dielectrics, and the validation of simulations of impurity diffusion. This overview of APT of semiconductors features research on metal-silicide contact formation and phase control, silicon field-effect transistors, and silicon and germanium nanowires. Work on silicide contacts to silicon is reviewed to demonstrate impurity characterization in small volumes and indicate how APT can facilitate defect mitigation and process optimization. Impurity contour analysis of a pFET semiconductor demonstrates the site-specificity that is achievable with current APTs and highlights complex device challenges that can be uniquely addressed. Finally, research on semiconducting nanowires and nanowire heterostructures demonstrates the potential for analysis of materials derived from bottom-up synthesis methods.In contrast, the combined high sensitivity (~5 × 10 17 cm −3 or 10 appm) and subnanometer-scale spatial resolution of atom-probe tomography (APT) suggest an important role for it in future device characterization. 1,2 APT measurements also have the potential to greatly improve modeling of processes; the availability of precise and accurate information at the atomic scale in 3D is extremely useful for calibrating and validating models of impurity atom implantation and diffusion.As decreasing device dimensions necessitate the industry to move from planar silicon device technology to more complex geometrical designs such as multigate transistors, fin-shaped field-effect transistors, and tri-gate transistors, the challenge of ensuring a specific impurity distribution, and thereby a well-defined charge distribution, increases greatly. To enable APT to analyze these complex structures, a combination of top-down and bottom-up sample preparation approaches have been developed, as illustrated in Figure 1. The availability of dual-beam focused ion beam (FIB) microscopy-based sample preparation methods 3,4 has enabled site-specific characterization of portions of the device structure under consideration (Figure 1c and 1d). The development of novel bottom-up approaches to nanowire growth 29 has enabled the analysis of nanowire specimens grown in place (Figure 1b).The TEM image of the device in cross section (Figure 1c) shows the materials diversity in a silicon device as revealed by the contrast differences. If the APT microtip is composed o...

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.

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