As an essential clock-system component, millimeter-wave dividers have been implemented for V-and W-band channels [1][2][3][4][5][6][7][8]. This has also served as a standard benchmark vehicle that reveals highspeed and low-power performances of a technology. Through technology scaling, CMOS CML static divider high-frequency performances have been scaled [6][7][8], and they are comparable to dividers in other technologies [1][2][3][4][5]. In addition to the device performance, circuit design and measurement determine the divider high-speed and wide frequency range performance. One of the uncertainties in CML static divider measurement is pulling and locking hysteresis. By using CML static divider topology, the divider has been assumed to have a fixed wide operation range, from DC to the f div,max , the maximum input-referred divider operational frequency. In fact, the CML static dividers show a certain degree of locking hysteresis, similar to injection-locking dividers [9]. When the circuit sensitivity curve is measured, it is not clear where to set the threshold. Depending on the method, a sensitivity curve can be optimistic or pessimistic. A similar problem lies in the f div,max , since it changes depending on the status of a divider. Also, there have not been any analytic results that can interpret the circuit parameters and performance, in spite of the common use of sensitivity curve in literatures.The CML static divider schematic is shown in Fig. 25.5.1. It has CML-based master-slave FF latches, with AC-coupled RF input and separate DC bias input. To maximize the divider performance, a cellbased FET layout is used with pitch relaxation. It effectively improves the device g m by enhancing the stress liner efficiency through the opening. The FET parasitic capacitance is reduced due to the increased gate-to-contact spacing. By its nature, the divider exhibits highly nonlinear behavior. It has multiplication as a singlebalanced mixer, and the circuit behaviors are quite different in selfoscillation and input-locked modes. An approximate and linearized circuit analysis is used to obtain sensitivity curve and locking hysteresis models. The approximation begins from the tail current i T modulation by input v I , and the resulting differential-pair g M,D changes. By assuming that the input is much smaller than the bias tail current I T , the modulated differential pair g M,D is derived with power series expansion and high-order term omission. The mixing is approximated by ignoring high-frequency terms with an assumption that they are low-pass filtered by the circuit [8]. The result will be more relevant to the high-frequency part of the divider operation due to the assumption. Another assumption is that the circuit is bistable between self-oscillation and input-locked modes. A steadystate circuit equation is established by assuming 270˚ phase between differential-pair input and output node v O . In the absence of input signal v I , the self-oscillation condition and frequency are obtained. The loading capacitance is ...
A 70GHz Manufacturable Complementary LC-VCO The VCO uses VDD=1.2V and the output spectrum is captured at with 6.14GHz Tuning Range in 65nm SOI CMOS Fig. 30.2.3. The peak frequency is -73.47GHz with -35dBm output power, and the marker phase-noise measurement is better than -92.9dBc/Hz at 1OMHz offset. The phase-noise measurement is lim-Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart2, ited by signal power and thermal noise floor. The oscillation fre-Choongyeun Cho', Weipeng Li3, Daihyun Lim4, Robert Trzcinski, quency of the same circuit with VCTRL sweep is shown in the right Mahender Kumar', Christine Norris', David Ahigren' plot. The circuit operates from the lowest tunable frequency fL=66.8 to the highest tunable f.=73.5GHz. The center frequency f0, aver-1IBIAR Hopewell Junction, N\lY age of fL and fH, is 70.1GHz. The FTR of the VCO is 6.68GHz, or IBeM T. J. Watson, Yorktown Heights, NY
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