A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology

Kim, D.D.; Cho, Choongyeun; Kim, Jonghae; Plouchart, J.-O.; Lim, Dokshin

doi:10.1109/csics.2008.50

Cited by 5 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For a reliable operation of any high-speed prescaler relatively high input power level is required, at least -15 dBm [36] (or even more for some 50 GHz devices [37]). Assuming a minimum acceptable value of the optical powers 30 dBm R P = − , taking ~3dBm S P + and 0.8 A/W = R , the power incident the amplifier following the photodiode is about -45 dBm provided no additional signal losses occur, e.g., due to polarization misalignment.…”

Section: Idea Of Laser Frequency Stabilizationmentioning

confidence: 99%

“…As the power of the optical reference signal becomes lower, the band-pass noise mentioned above starts to influence the prescaler more and more, and becomes a source of frequency errors when the frequency is estimated by counting the number of cycles within the reference time interval. It should be emphasized that this phenomenon, which requires the presence of relatively strong noise at the input of the prescaler, differs substantially from a well-known self-oscillation of prescalers that occurs at low input powers [36], [38]. As up to authors' knowledge there is no good theory explaining the observed effect and allowing predicting occurring frequency error [39], [40], we decided to perform a set of experiments, where the photodiode (see Fig.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Synchronized Laser Modules With Frequency Offset up to 50 GHz for Ultra-Accurate Long-Distance Fiber Optic Time Transfer Links

Śliwczyński

Krehlik

Buczek

et al. 2022

J. Lightwave Technol.

View full text Add to dashboard Cite

The paper is focused on a systematic investigation of the circuits for active stabilization of the frequency offset between two semiconductor lasers in ultra-accurate fiber optic time transfer systems. The frequency offset is increased up to 50 GHz, which can be achieved not only with relatively low-noise integrated tunable laser assemblies, but also with ordinary, telecomgrade, distributed feedback lasers. The paper starts by determining the general frequency accuracy and stability, required to keep the uncertainty contribution of the stabilization circuit at a negligible level (assumed here as 1 ps) compared to other contributions of the overall uncertainty of the link calibration. Next, the technical details of the essential building block of the system discussed, which is required to convert the high-frequency offset to lower frequencies to allow convenient frequency measurement, are analyzed. Experimental circuits built with commercially available millimeter wave integrated circuits were tested with the frequency offset complying with telecom dense wavelength division multiplex standards, equal to 12.5 GHz, 25 GHz and 50 GHz. It was found that such stabilization circuits can cause substantial systematic errors, which are related to lasers' phase noise and the operation with low input optical powers (below -39 dBm in evaluated circuits). These effects were investigated experimentally in detail and countermeasures were proposed.

show abstract

Section: Idea Of Laser Frequency Stabilizationmentioning

confidence: 99%

mentioning

confidence: 99%

Synchronized Laser Modules With Frequency Offset up to 50 GHz for Ultra-Accurate Long-Distance Fiber Optic Time Transfer Links

Śliwczyński

Krehlik

Buczek

et al. 2022

J. Lightwave Technol.

View full text Add to dashboard Cite

show abstract

“…Each latch is based on CML which is characterized by small voltage swings and fully differential architecture. SFDs, although known for a long time, have only been demonstrated at mm‐wave frequencies recently through various circuit optimizations or specialized technologies . Each D‐latch consists of a tracking or sampling pair ( M 1 , M 2 and M 8 , M 9 ) and a latching pair ( M 3 , M 4 and M 10 , M 11 ).…”

Section: Circuit Designmentioning

confidence: 99%

A low-power 802.11 ad compatible 60-GHz phase-locked loop in 65-nm CMOS

Cheema

Arsalan

Salama

et al. 2015

Microw. Opt. Technol. Lett.

View full text Add to dashboard Cite

A 60‐GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system‐on‐chip transmitter with on‐chip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance contributions in the voltage controlled oscillator enables the coverage of the complete 802.11 ad frequency band from 57.2 to 65.8 GHz. A new 4‐stage distribution network supplying the local oscillator (LO) signal to the mixer, the feedback loop and the external equipment is introduced. The prescaler based on the static frequency division approach is enhanced using shunt‐peaking and asymmetric capacitive loading. The current mode logic based divider chain is optimized for low power and minimum silicon foot‐print. A dead‐zone free phase frequency detector, low leakage charge pump, and an integrated second‐order passive filter completes the feedback loop. The PLL implemented in 65 nm CMOS process occupies only 0.6 mm2 of chip space and has a measured locking range from 56.8 to 66.5 GHz. The reference spurs are lower than −40 dBc and the in‐band and out‐of‐band phase noise is −88.12 dBc/Hz and −117 dBc/Hz, respectively. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:660–667, 2015

show abstract

An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices

Tibenszky

Carta

Ellinger

2021

Electronics Letters

View full text Add to dashboard Cite

The idea to use a lower threshold, but slightly slower transistor over the fastest transistor type for large‐signal circuits is presented with experimental verification for a compact divide‐by‐4 true single phase clock (TSPC) frequency divider. The use of the lowest threshold PMOS devices resulted in self‐resonance frequencies of 41.7, 56, and 60 GHz at supply voltages of 0.5, 0.8 and 0.9 V, respectively. Compared to a divider of the same architecture in the same technology, but with higher threshold voltage devices, this corresponds to improvements of 67%, 33% and 27%, respectively. Power consumptions of 26 and 355 μW were measured for a 20 GHz and a 70 GHz input signal for supply voltages of 0.5 and 0.9 V, respectively. The best knowledge of the authors, these results are the best reported to date for TSPC divider architecture, and they compete with state of the art for inductorless current‐mode logic dividers.

show abstract

A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology

Cited by 5 publications

References 12 publications

Synchronized Laser Modules With Frequency Offset up to 50 GHz for Ultra-Accurate Long-Distance Fiber Optic Time Transfer Links

Synchronized Laser Modules With Frequency Offset up to 50 GHz for Ultra-Accurate Long-Distance Fiber Optic Time Transfer Links

A low-power 802.11 ad compatible 60-GHz phase-locked loop in 65-nm CMOS

An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices

Contact Info

Product

Resources

About