This Letter presents a millimetre‐wave CMOS oscillator, which achieves 4.9 dBm output power with 16% peak power efficiency. A phase noise of −98 thinmathspacedBc/Hz at 1 MHz offset frequency and 26.7% tuning range around 57.5 GHz centre frequency were verified experimentally. To the best knowledge of the authors, the output power, efficiency, and phase noise performance are the best among fundamental CMOS oscillators in the frequency range of interest, while the tuning range is the third highest result reported to date. The circuit occupies a silicon area of ∼9000 thinmathspaceμnormalm2 without the matching inductors on a 22 nm fully depleted silicon on insulator (FD‐SOI) CMOS technology.
The idea to use a lower threshold, but slightly slower transistor over the fastest transistor type for large‐signal circuits is presented with experimental verification for a compact divide‐by‐4 true single phase clock (TSPC) frequency divider. The use of the lowest threshold PMOS devices resulted in self‐resonance frequencies of 41.7, 56, and 60 GHz at supply voltages of 0.5, 0.8 and 0.9 V, respectively. Compared to a divider of the same architecture in the same technology, but with higher threshold voltage devices, this corresponds to improvements of 67%, 33% and 27%, respectively. Power consumptions of 26 and 355 μW were measured for a 20 GHz and a 70 GHz input signal for supply voltages of 0.5 and 0.9 V, respectively. The best knowledge of the authors, these results are the best reported to date for TSPC divider architecture, and they compete with state of the art for inductorless current‐mode logic dividers.
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