Abstract:A 60‐GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system‐on‐chip transmitter with on‐chip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance contributions in the voltage controlled oscillator enables the coverage of the… Show more
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