Wideband mmWave CML static divider in 65nm SOI CMOS technology

Kim, D.D.; Cho, Choongyeun; Kim, Jonghae; Plouchart, J.-O.

doi:10.1109/cicc.2008.4672164

Cited by 12 publications

(3 citation statements)

References 30 publications

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“…Input capacitors C1 and C2 are 200fF vertical natural capacitors made with all digital routing metal layers except lowest one to reduce signal leakage to substrate. Detailed analysis and design of this topology is presented in many publications such as [3], [4] and [5]. In this paper, we focus mostly on critical aspects of the layout design.…”

Section: Frequency Divider Circuit Designmentioning

confidence: 99%

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Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI

Hietanen

Aikio

Sethi

et al. 2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Two mmWave frequency dividers were designed, manufactured and measured using static current mode logic divider topology on 45nm CMOS PD-SOI technology. Dividers differ by flip-flop load, first divider uses resistive loads and second divider active PMOS loads. Achieved output referred frequency ranges cover 13-22GHz on the first divider and 8-23GHz on the second divider. Both dividers occupy small areas of 0.002mm², and 0.0017mm², respectively and dissipate only 10.3mW and 11mW from 1V supply. The broad tuning range, moderate speed, small area and I/Q output phases make this divider architecture an attractive option for sliding-IF transceiver topologies operating up to 69GHz carrier frequency and enable operation of PLL's up to 46GHz.

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Section: Frequency Divider Circuit Designmentioning

confidence: 99%

“…Wideband I/Q generation enables efficient sliding IF topologies because generating I/Q phases with dedicated circuits like polyphase filters require large area and significant power for loss compensating buffers [2]. [3], [4]. This paper presents two static current mode logic (CML) dividers operating at mmWave frequencies.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI

Hietanen

Aikio

Sethi

et al. 2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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show abstract

“…This method fails to explain the self-oscillation and the existence of the lower limit of operation frequency. The work in [6] models the CML divider as a single-balanced mixer and with steady-complex analysis at output frequency but fails to explain the upper limit of the locking range. The work in [7] presents a novel insight based on injection-locking phenomena but does not detail the analysis of working conditions.…”

Section: Introductionmentioning

confidence: 99%

Geometric Analysis and Systematic Design of Millimeter-Wave Low-Power Frequency Dividers in 65-nm CMOS

Zhu

Zhao

2020

IEEE Access

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Broadband current-mode logic static divide-by-2 and divide-by-4 circuits fabricated in 65-nm CMOS are presented. The low-power frequency dividers are analyzed in a geometric way. The selfoscillation frequency and locking range of current-mode dividers are analyzed based on current vectors. A systematic design methodology is proposed to reduce power consumption and enhance the locking range. The divide-by-2 circuit operates from 8 to 40 GHz with 0 dBm input signal and consumes dc power of 4.6 mW with a 1.0 V supply. The divide-by-4 circuit operates from 12.4 to 38.4 GHz with 0 dBm input signal and consumes dc power of 7.5 mW with a 1.0 V supply. The core areas of divide-by-2/4 circuits are only 25 × 33 µm 2 and 47 × 28 µm 2 respectively.

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High-speed digital logic

2013

High-Frequency Integrated Circuits

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Wideband mmWave CML static divider in 65nm SOI CMOS technology

Cited by 12 publications

References 30 publications

Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI

Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI

Geometric Analysis and Systematic Design of Millimeter-Wave Low-Power Frequency Dividers in 65-nm CMOS

High-speed digital logic

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