Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI

Hietanen, Mikko; Aikio, Janne; Sethi, Alok; Akbar, Rehman; Rahkonen, Timo; Pärssinen, Aarno

doi:10.1109/norchip.2019.8906899

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B the Small Signal Gain Of Ring Oscillator1

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“…Substitute formula (7) into (12) and (13). We get that (12) and (13) are equivalent at the self-oscillation frequency.…”

Section: B the Small Signal Gain Of Ring Oscillatormentioning

confidence: 97%

Geometric Analysis and Systematic Design of Millimeter-Wave Low-Power Frequency Dividers in 65-nm CMOS

Zhu

Zhao

2020

IEEE Access

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Broadband current-mode logic static divide-by-2 and divide-by-4 circuits fabricated in 65-nm CMOS are presented. The low-power frequency dividers are analyzed in a geometric way. The selfoscillation frequency and locking range of current-mode dividers are analyzed based on current vectors. A systematic design methodology is proposed to reduce power consumption and enhance the locking range. The divide-by-2 circuit operates from 8 to 40 GHz with 0 dBm input signal and consumes dc power of 4.6 mW with a 1.0 V supply. The divide-by-4 circuit operates from 12.4 to 38.4 GHz with 0 dBm input signal and consumes dc power of 7.5 mW with a 1.0 V supply. The core areas of divide-by-2/4 circuits are only 25 × 33 µm 2 and 47 × 28 µm 2 respectively.

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“…Substitute formula (7) into (12) and (13). We get that (12) and (13) are equivalent at the self-oscillation frequency.…”

Section: B the Small Signal Gain Of Ring Oscillatormentioning

confidence: 97%