Geometric Analysis and Systematic Design of Millimeter-Wave Low-Power Frequency Dividers in 65-nm CMOS

Abstract

Broadband current-mode logic static divide-by-2 and divide-by-4 circuits fabricated in 65-nm CMOS are presented. The low-power frequency dividers are analyzed in a geometric way. The selfoscillation frequency and locking range of current-mode dividers are analyzed based on current vectors. A systematic design methodology is proposed to reduce power consumption and enhance the locking range. The divide-by-2 circuit operates from 8 to 40 GHz with 0 dBm input signal and consumes dc power of 4.6 mW with a 1.0 V supply. The divide-by-4 circuit operates from 12.4 to 38.4 GHz with 0 dBm input signal and consumes dc power of 7.5 mW with a 1.0 V supply. The core areas of divide-by-2/4 circuits are only 25 × 33 µm 2 and 47 × 28 µm 2 respectively.

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

“…Equation ( 18) means that the cross-coupled M L transistors should generate a smallsignal equivalent negative resistance able to compensate the losses due to the load resistors R D . It is also worth presenting the mathematical expression of f SO reported in [53] in the case of a Frequency Divider constituted by n latches, where n is even. (20) where |I LSO | and |I DSO | are the modules of the phasors, rotating at 2πf SO pulsation, of the currents flowing in the M D and M L transistors, respectively, under the self-oscillation condition.…”

“…Figure 8 compares self-oscillation waveforms and the sensitivity curves for the Frequency Divider simulated at 300 K and 4 K. The self-oscillation frequency shifts from 13.6 GHz to 15.6 GHz when the temperature drops from 300 K to 4 K. Since fSO is inversely proportional to the time constant RCPAR, (see Equations ( 19)-( 21)), to investigate the fSO shift induced by the temperature change it is useful to get a rough estimation of this time constant. Following [53] the parasitic capacitance CPAR was estimated as sum of several contributes. Focusing on the node in Figure 8 In this expression, CDB,D1 and CGD,D1 are the drain-bulk and the overlap gate-drain capacitances, respectively, of the MD1 transistor, CGD,L1 and CGS,L1 are the overlap gate-drain and gate-source capacitances of the ML1 transistor, CGD,L2 is the overlap gate-drain capacitance for the ML2 transistor, COX,L1 is the gate oxide capacitance of the ML1 transistor and CLOAD is the capacitive load provided by the input node of the following register.…”

“…Since f SO is inversely proportional to the time constant RC PAR , (see Equations ( 19)-( 21)), to investigate the f SO shift induced by the temperature change it is useful to get a rough estimation of this time constant. Following [53] the parasitic capacitance C PAR was estimated as sum of several contributes. Focusing on the Q node in Figure 8, one can write:…”