The influence of the SIN cap-layer deposition process including different pre-clean treatments on the electromigration (EM) and stressvoiding (SV) behavior of copper dual damascene metalli:rations has been studied. A rcmarkable trade-off between the EM and SV performance was revealed depcnding primarily on the pre-treatment beforc cap-layer deposition rather than the deposition process itself On the one hand an "aggressive" pre-treatment yields improved CdSiN-interface properties with higher electromigration failure times and activation energies (1.22 ... 1.26eV). On the other hand these pre-cleans were found to provoke stressvoiding failures because of the recovery of crystal defects induced in the hulk copper during the plasma treatment. The degree of microstructural damage and hence thc SV susceptibility was found to increase with the preclean intensity. In contrast, no SV risk is related to "less aggressive" pre-clean treatments since they are influencing only the copper surface. The crystal structure of the bulk remains unaffected and hence -in absence of any crystal recovery -no vacancies will be generated. However, these pre-cleans result in significantly lower EM performance with smaller failure times and activation energies (1.03 ... 1.06eV).The results illustrate the need to adjust the SIN cap-layer process parameters with respect to both EM & SV performance to meet the overall reliability requirements for these wear-out mechanisms: at the same time.
Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An altemate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.
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