Finite element modeling of thermo-mechanical reliability of a Bumpless Flip Chip Package (BFCP) was investigated. Both package-level and board-level assemblies are modeled using 2-D plane strain models. The package-level temperature cycliing profile used was -65C to +150C, with 2 cycleshour, upper and lower soak time of 10 minutes. The package survived 2000 cycles without any failures. The board level assembly test is planned and modeling is conducted for a temperature cycling profile of -4OC to +125C, with 1 cyclelhour, upper and lower soak time of 15 minutes.For the package level analysis, the copper interconnection material properties were modeled using different properties from bulk Cu and electroplated Cu data. The mechanical properties of both the bulk and electroplated copper were used in the FEA simulation and the results compared. Fatigue life prediction study, using the appropriate thin-film propzrties of copper and the fatigue properties of thin-film copper gave reasonable predicted life.For the second level solder joint analysis, the deformation behavior of the compliant terminals with the solder joints were investigated. Visco-elastic properties was used for the epoxy resin, viscoplastic properties was used for the eutectic Sn-Pb solder joints. The in elastic energy density method was used for solder joint fatigue life prediction.
Redistribution layer (RDL) is an integral part of 3D IC integration, especially for 2.5D IC integration with a passive interposer. The RDL allows for circuitry fan-outs of and allows for lateral communication between the chips attached to the interposer. There are at least two ways to fabricate the RDL, namely (1) polymers to make the passivation and Cu-plating to make the metal layer, and (2) semiconductor back-end-of-line Cu damascene. In this study, the materials and processes of these methods are presented. Emphasis is placed on the Cu damascene method.
The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.
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