Finite element modeling of thermo-mechanical reliability of a Bumpless Flip Chip Package (BFCP) was investigated. Both package-level and board-level assemblies are modeled using 2-D plane strain models. The package-level temperature cycliing profile used was -65C to +150C, with 2 cycleshour, upper and lower soak time of 10 minutes. The package survived 2000 cycles without any failures. The board level assembly test is planned and modeling is conducted for a temperature cycling profile of -4OC to +125C, with 1 cyclelhour, upper and lower soak time of 15 minutes.For the package level analysis, the copper interconnection material properties were modeled using different properties from bulk Cu and electroplated Cu data. The mechanical properties of both the bulk and electroplated copper were used in the FEA simulation and the results compared. Fatigue life prediction study, using the appropriate thin-film propzrties of copper and the fatigue properties of thin-film copper gave reasonable predicted life.For the second level solder joint analysis, the deformation behavior of the compliant terminals with the solder joints were investigated. Visco-elastic properties was used for the epoxy resin, viscoplastic properties was used for the eutectic Sn-Pb solder joints. The in elastic energy density method was used for solder joint fatigue life prediction.
Current flip chip packaging activities are divided into two very different approaches. One is to further improve the bumped structure with particular focus on bump structure, lead-free, under-fill material and board level reliability issues. The other is to develop the ultimate structurdwithout bumps to achieve even better electrical characteristics and meet more stringent environmental specifications.This paper presents a novel bumpless flip chip package for costlperformance driven devices. Using the electrochemical plating (ECP) method, a pattem of tine-line traces down to 25 pm lineispace is fabricated and connected to the die pads directly without using wire-bonds or solder bumps or an interposer substrate or vacuum processes such as thin film sputtering. This method enables the production of area array packages up to 256 I10 using a single layer of metal.Package-to-board level connection is made through a series of resin-tilled terminals which provide excellent mechanical compliancy between the package and the assembled board. The electroplated fine-line traces which provide signal re-distribution in this package are similar to those in wafer level packages. More importantly, their "fanout" feature is the key to enabling high lead count devices to be accommodated in the area array format with this package.Details of the design concepts and processing technology associated with this package are discussed. Considerations for various costlperformance devices are discussed. Finally, the importance of design integration early in the technology development cycle with package-level and board-level reliability is highlighted as a critical path to an optimal design for cost-driven and/or performance-driven devices. IntroductionThe key factors driving semiconductor integrated circuit
Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chipstacking technology have received a great number of attentions.
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