2012 IEEE 62nd Electronic Components and Technology Conference 2012
DOI: 10.1109/ectc.2012.6249060
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Low temperature bonding using non-conductive adhesive for 3D chip stacking with 30μm-pitch micro solder bump interconnections

Abstract: Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chipstacking technology have received a great number of attentions.

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Cited by 6 publications
(2 citation statements)
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“…However, the high bonding temperature during stacking process may lead to chip warpage caused by the mismatch of coefficient of thermal expansion among each structure of the chip. Furthermore, the warpage may also lead to stress concentration that will damage the chip [5,6]. Thus, many researches have been focused on the low temperature bonding technologies [6][7][8].…”
Section: Introductionmentioning
confidence: 99%
“…However, the high bonding temperature during stacking process may lead to chip warpage caused by the mismatch of coefficient of thermal expansion among each structure of the chip. Furthermore, the warpage may also lead to stress concentration that will damage the chip [5,6]. Thus, many researches have been focused on the low temperature bonding technologies [6][7][8].…”
Section: Introductionmentioning
confidence: 99%
“…Snap curing time of NCA should be considered to improve productivity in the flip-chip bonding process, which is to bond between Si chip and substrate one by one [16,17]. Additionally, hightemperature thermo-compression is accompanied by the bonding process, which causes substrate softening and the joint deterioration [18,19]. Therefore, the shear strength for interconnection between a chip and a substrate affects the reliability of the package.…”
Section: Introductionmentioning
confidence: 99%