Redistribution Layers (RDLs) for 2.5D/3D IC Integration

Lau, John H.; Tzeng, P.; Lee, C.; Zhan, Cheng; Li, M.; Cline, J.; Saito, K.; Hsin, Y.; Chang, P.; Chang, Y.; Chen, J.; Chen, S.; Wu, C.; Chang, H.; Chien, Chun-Hsien; Lin, Curry; Ku, T.; Lo, R.; Kao, Ming-Jer

doi:10.4071/imaps.406

Cited by 39 publications

(4 citation statements)

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“…Redistribution layers [104][105][106][107] are the most integral part of wafer-level packaging (WLP). The RDL consists of two layers, the dielectric layer and the Cu conducting layer.…”

Section: Redistribution Layers Fabricationsmentioning

confidence: 99%

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Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…Redistribution layers [104][105][106][107] are the most integral part of wafer-level packaging (WLP). The RDL consists of two layers, the dielectric layer and the Cu conducting layer.…”

Section: Redistribution Layers Fabricationsmentioning

confidence: 99%

“…29. This is called the dual Cu-damascene method [104,105]. Finally, repeat all the processes to get the other RDLs.…”

Section: Journal Of Electronic Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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“…It can be observed that the interposer is supporting these two chips on its top and bottom sides. In this case, the size of the interposer can be smaller (or more chips can be placed on the same size of interposer), and the electrical performance can be better because the chip-to-chip interconnects are face-to-face instead of side-to-side [13]- [22]. In addition, it is truly a 3-D IC integration with a passive interposer, which will be the focus of this paper.…”

Section: Introductionmentioning

confidence: 99%

Through-Silicon Hole Interposers for 3-D IC Integration

Lau

Lee

Zhan

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

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“…Thus, the RDL process has become more critical with the improvement of packaging technology. [1][2][3][4][5] In a conventional RDL process, that is, a semi-additive process (SAP), 6 the Cu seed layer exists only at the bottom of the photoresist (PR) pattern; hence, Cu was only deposited at the bottom of the pattern by electrodeposition. After the Cu deposition, the PR patterns were removed by PR strip process, and the Cu seed layer under the PR pattern was removed by wet etching.…”

mentioning

confidence: 99%

Selective Copper Electrodeposition for Redistribution Layer by Varying Concentration and Agitation of Janus Green B

Lee,

Kim,

Han

et al. 2023

ECS J. Solid State Sci. Technol.

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A fine-pitch redistribution layer (RDL) for high-performance devices in a fan-out wafer-level package (FOWLP) is required in semiconductor packaging technology. The damascene process for fine-pitch RDL has been studied for several years, which has been introduced to overcome the etching problems. Although surface planarization for removing overburden is necessary for the damascene process in RDL, it adds high cost to the FOWLP process. Selective Cu electrodeposition is a method used to prevent overburden. Janus Green B (JGB) is utilized as a leveler in Cu electrodeposition and has properties that depend on concentration and agitation. These properties affected the Cu deposition rate according to the pattern position. Thus, the electrochemical properties of JGB were investigated based on the concentration of JGB and agitation. Furthermore, the effect of JGB on the crystalline structure of the Cu film was examined. Additionally, changes in the growth behavior of the Cu nuclei caused by JGB were observed during the initial stage of chronoamperometry. Based on these results, selective Cu electrodeposition was successfully performed on the patterned substrate using the difference in the concentration of JGB and agitation.

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Redistribution Layers (RDLs) for 2.5D/3D IC Integration

Cited by 39 publications

References 0 publications

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Through-Silicon Hole Interposers for 3-D IC Integration

Selective Copper Electrodeposition for Redistribution Layer by Varying Concentration and Agitation of Janus Green B

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