Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Abstract

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

“…Thermal management has long been considered as one of the keys to maximize device performance and reliability. Compared to conventional MCPs (multichip packages) and SIP (system in package), advanced heterogeneous packages face more challenges in thermal management due to the targeted finer pitches, 3D stacks, more inputs/outputs (I/Os), higher densities, higher power consumptions, and higher performance applications [78][79][80][81].…”

“…Thermal management challenge is mostly driven by the continuous increase in power density. Many of the 2.5D package platforms use a silicon interposer to interconnect logic chips and HBMs [78][79][80]88,93], which have a high heat flux more than 100 W Á cm À2 in a single package [81,104,105]. This requires effective cooling very close to the heat source.…”

Sodium Metasilicate-Based Inorganic Composite for Heterogeneous Integration of Microsystems

“…[8]- [13] Molding is of particular interest as it is commonly used in fan-out wafer level packaging (FOWLP) and fanout panel level packaging (FOPLP) to integrate and encapsulate commercial off the shelf (COTS) components into high density packages. [2], [14], [15] Ultimately, epoxy molding compounds (EMC) have the potential to enable components to be heterogeneously 3D-integrated into highly capable microsystems that benefit from 3D integration without needing components to be specially designed for it. Common commercial EMC have coefficients of thermal expansion (CTE) of around 10 ppm/ • C [14], with some EMC in literature reporting CTE of approximately 6 ppm/ • C [16], and glass transition temperatures (T g ) ranging from 130 • C-200 • C. [16], [17] However, these EMC face considerable challenges due to CTE mismatch and low T g that lead to warpage, thermal stress build up, component shifting, and ultimately, strict limitations on processing temperatures after the post mold cure (PMC).…”

“…[2], [14], [15] Ultimately, epoxy molding compounds (EMC) have the potential to enable components to be heterogeneously 3D-integrated into highly capable microsystems that benefit from 3D integration without needing components to be specially designed for it. Common commercial EMC have coefficients of thermal expansion (CTE) of around 10 ppm/ • C [14], with some EMC in literature reporting CTE of approximately 6 ppm/ • C [16], and glass transition temperatures (T g ) ranging from 130 • C-200 • C. [16], [17] However, these EMC face considerable challenges due to CTE mismatch and low T g that lead to warpage, thermal stress build up, component shifting, and ultimately, strict limitations on processing temperatures after the post mold cure (PMC). [2], [14]- [21] Therefore, for a molding material to support this heterogeneous 3D integration approach, it must meet the following criteria:…”

Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness

“…Copper pillars based advanced bump has the smallest interconnect pitch being limited to 40 μm, i.e., a 25 μm Cu bump with 15 μm spacing. To further shrink the Cu bump pitch, a strict surface nanoscale flatness is necessary [ 3 ]. The second mainstream method is the bumpless approach which eliminates the need for intermediate conductive bump and a much reduced interconnect pitch down to 2 μm or lower becomes possible, if the roughness of the interconnecting surfaces is reduced to below 0.1 nm via CMP (chemical mechanical polishing).…”