We report recent advances in tool and process hardening of a first of its kind 300 mm wafer-to-wafer (WtW) preprocessing, aligning, and bonding integrated tool. We have demonstrated sub-500 nm post-bond alignment accuracies for 300 mm WtW face-to-face (FtF) Cu-Cu thermocompression bonds, WtW FtF Si-Si fusion bonds, and WtW FtF oxideoxide fusion bonds. All process of record (POR) recipes that were developed had undetectable voids based on scanning acoustic microscope (C-SAM) measurements on representative bonded Cu, oxide, and Si blanket wafers. Optimized bonded patterned wafer splits in the Cu-Cu WtW thermocompression bonding step have shown alignment accuracies down to ~190 nm, the highest accuracy to date. Using an infraredenabled, high speed focused ion beam (FIB) system (with XeF 2 ) with a CAD overlay function to assist in selective sample preparation, we have verified that the bonding interfaces at the via chain structures with 1-5 μm diameter vias show no interfacial voids. Also, there is evidence of Cu interdiffusion, as supported by transmission electron microscopy (TEM) and electron backscattering diffraction (EBSD) data.
IntroductionImmediate efforts to bridge high volume manufacturing (HVM) readiness gaps in wafer-to-wafer (WtW) bonding and face-to-face (FtF) alignment technologies are necessary to create 3D integrated circuit (3DIC) products. 3DIC integration technology, the process of vertically stacking multiple processed wafers containing ICs by electrically connecting them in the z-direction, has been attracting considerable attention because it may allow not only performance improvements as a result of the significant decrease in total interconnect length, but also defect-free heterogeneous integration for future high performance products. Examples of 3D stacking demonstrations from the industry and research laboratories include 330 mm WtW stacking by Cu bonding with strainedSi/low-k 65 nm CMOS technology using Cu through silicon vias (TSVs) to access the bonded NMOS/PMOS circuits for
The semiconductor industry has seen tremendous progress over the last few decades with continuous reduction in transistor size to improve device performance. Miniaturization of devices has led to changes in the dopants and dielectric layers incorporated. As the gradual shift from two-dimensional metal-oxide semiconductor field-effect transistor to three-dimensional (3D) field-effect transistors (finFETs) occurred, it has become imperative to understand compositional variability with nanoscale spatial resolution. Compositional changes can affect device performance primarily through fluctuations in threshold voltage and channel current density. Traditional techniques such as scanning electron microscope and focused ion beam no longer provide the required resolution to probe the physical structure and chemical composition of individual fins. Hence advanced multimodal characterization approaches are required to better understand electronic devices. Herein, we report the study of 14 nm commercial finFETs using atom probe tomography (APT) and scanning transmission electron microscopy-energy-dispersive X-ray spectroscopy (STEM-EDS). Complimentary compositional maps were obtained using both techniques with analysis of the gate dielectrics and silicon fin. APT additionally provided 3D information and allowed analysis of the distribution of low atomic number dopant elements (e.g., boron), which are elusive when using STEM-EDS.
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