The black border is a frame created by removing all the multilayers on the EUV mask in the region around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a wafer. Papers have documented its effectiveness [1] . As the technology transitions into manufacturing, the black border must be optimized from the initial mask making process through its life. In this work, the black border is evaluated in three stages: the black border during fabrication, the final sidewall profile, and extended lifetime studies.This work evaluates the black border through simulations and physical experiments. The simulations address concerns for defects and sidewall profiles. The physical experiments test the current black border process. Three masks are used: one mask to test how black border affects the image placement of features on mask and two masks to test how the multilayers change through extended cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images and simulated wafer effects.By evaluating the black border from both a mask making perspective and a lifetime perspective, we are able to characterize how the structure evolves. The mask data and simulations together predict the performance of the black border and its ability to maintain critical dimensions on wafer. In this paper we explore what mask changes occur and how they will affect mask use.
Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM). 1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable. 3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing.In this work, we assess mutltiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.
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