The low thermal conductivity of Ga 2 O 3 has arguably been the most serious concern for Ga 2 O 3 power and RF devices. Despite many simulation studies, there is no experimental report on the thermal resistance of a large-area, packaged Ga 2 O 3 device. This work fills this gap by demonstrating a 15-A double-side packaged Ga 2 O 3 Schottky barrier diode (SBD) and measuring its junctionto-case thermal resistance (R θJC ) in the bottom-side-and junction-side-cooling configurations. The R θJC characterization is based on the transient dual interface method, i.e., JEDEC 51-14 standard. The R θJC of the junction-and bottom-cooled Ga 2 O 3 SBD was measured to be 0.5 K/W and 1.43 K/W, respectively, with the former R θJC lower than that of similarly-rated commercial SiC SBDs. This low R θJC is attributable to the heat extraction directly from the Schottky junction instead of through the Ga 2 O 3 chip. The R θJC lower than that of commercial SiC devices proves the viability of Ga 2 O 3 devices for high-power applications and manifest the significance of proper packaging for their thermal management.

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Wide-bandgap power devices with voltage ratings exceeding 10 kV have the potential to revolutionize medium-and high-voltage systems due to their high-speed switching and lower on-state losses. However, present power module packages are limiting the performance of these unique switches. The objective of this work is to push the boundaries of high-density, high-speed, 10 kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the more recent and prominent electrostatic and electromagnetic interference issues associated with high-speed, 10 kV devices. The module achieves low and balanced parasitic inductances, resulting in a record switching speed of 250 V/ns with negligible ringing and voltage overshoot. An integrated screen reduces the commonmode current that is generated by these fast voltage transients by ten times. This screen connection simultaneously increases the partial discharge inception voltage by more than 50 %. A compact, medium-voltage termination and system interface design is also proposed in this work. With the integrated jet-impingement cooler, the power module prototype achieves a power density of 4 W/mm 3 . This paper presents the design, prototyping, and testing of this optimized package for 10 kV SiC MOSFETs.

The advancement of silicon carbide (SiC) power devices with voltage ratings exceeding 10 kV is expected to revolutionize medium-and high-voltage systems. However, present power module packages are limiting the performance of these unique switches. The objective of this research is to push the boundaries of high-density, high-speed, 10 kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the more recent and prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10 kV devices. The high-speed switching and high voltage rating of these devices causes significant EMI and high electric field. Existing power module packages are unable to address these challenges, resulting in detrimental EMI and partial discharge that limit the converter operation. This paper presents the design and testing of a 10 kV SiC MOSFET power module that switches at a record 250 V/ns without compromising the signal and ground integrity due to an integrated screen reduces the common-mode current by ten times. This screen connection simultaneously increases the partial discharge inception voltage by more than 50 %. With the integrated cooling system, the power module prototype achieves a power density of 4 W/mm 3 . 1

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Power semiconductor device is a fundamental driver for advancement in power electronics, the technology for electric energy conversion. Power devices based on wide-bandgap (WBG) and ultra-wide bandgap (UWBG) semiconductors allow for smaller chip size, lower loss and higher frequency as compared to the silicon (Si) counterpart, thus enabling a higher system efficiency and smaller form factor. Amongst the challenges for the development and deployment of WBG and UWBG devices is the efficient dissipation of heat, an unavoidable by-product of the higher power density. To mitigate the performance limitations and reliability issues caused by self-heating, thermal management is required at both device and package levels. Particularly, packaging is a crucial milestone for the development of any power device technology; WBG and UWBG devices have both reached this milestone recently. This paper provides a timely review on the thermal management of WBG and UWBG power devices with an emphasis on the packaged devices. Additionally, emerging UWBG devices hold good promise for high-temperature applications due to the low intrinsic carrier density and the increased dopant ionization at elevated temperatures. The fulfillment of this promise in system applications, in conjunction with overcoming the thermal limitations of some UWBG materials, require new thermal management and packaging technologies. To this end, we provide perspectives on the relevant challenges, potential solutions and research opportunities, highlighting the pressing needs for the device-package, electro-thermal co-design and the high-temperature packages that can withstand the high electric field expected in UWBG devices.

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