High-performance polycrystalline silicon thin-film transistors ͑poly-Si TFTs͒ integrating high-Pr 2 O 3 gate dielectric and fluorinepassivated poly-Si film are demonstrated. High gate capacitance density and thin equivalent-oxide thickness provided by the high-Pr 2 O 3 gate dielectric have the advantage of increasing the driving current capability of the TFT device, but an undesirable off-state leakage current could be introduced from the high electric field near the drain side. Introducing fluorine atoms into poly-Si films by employing a low-temperature CF 4 plasma treatment can effectively passivate the trap states. With 10 W CF 4 plasma treatment on poly-Si film, the electrical characteristics of poly-Si Pr 2 O 3 TFTs can be significantly improved, including a steeper subthreshold swing, smaller threshold voltage, higher field-effect mobility, and better on/off current ratio compared with that without CF 4 plasma treatment. The maximum off-state leakage current of the fluorine-passivated TFT is more than one order of magnitude lower than that of the control TFT. Furthermore, the incorporation of fluorine atoms by CF 4 plasma treatment also improves the reliability of poly-Si Pr 2 O 3 TFTs against hot carrier stressing, which is due to the formation of stronger Si-F bonds in place of weak Si-H bonds in the poly-Si channel and at the Pr 2 O 3 gate dielectric/poly-Si interface. Therefore, high-performance and high-reliability poly-Si TFTs with Pr 2 O 3 gate dielectric and CF 4 plasma treatment on poly-Si film are suitable for activematrix liquid crystal display application.
To overcome the offset voltage (V OS ) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-m LTPS technology. Using the offset compensation technique, the V OS of output buffer can be controlled within 100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel.
In this study, we demonstrate the stability of high-La 2 O 3 metal-insulator-metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance () decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of .Additionally, high stability of 10-year lifetime is achieved for a 10-nm La 2 O 3 MIM capacitor with an 11.4 fF/mm 2 capacitance density.
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