The imprint of a ferroelectric thin film capacitor is studied using an improved model consisting of two nonswitching thin interface layers near the top and bottom electrodes. The difference in electrical conductivity between the two interface layers induces voltage offset and deformation behaviors in hysteresis loops. Size dependence of shift effect of Bi4−xNdxTi3O12 thin film is explained qualitatively by taking into account the thickness ratio of the interface layer and the bulk film. Various shifts and anamorphic shapes with different electrodes and processes have been effectively reproduced through changing the layer conductivities. The simulated shifted hysteresis loops agree well with the experiment. Theoretical prediction based on this approach may provide a method to reduce imprint failure.
The electrical properties of negative capacitance (NC) ferroelectric field-effect transistors (FeFETs) were theoretically investigated in the temperature range from 280 to 360 K. The derived results indicate that for a fixed thickness of ferroelectric thin film the amplification of surface potential can be tuned by temperature. The transfer and output characteristics degrade with increasing temperature due to the gradual loss of ferroelectric NC effect. It is expected that the derived results may provide some insight into the design and performance improvement for the low power dissipation applications of FeFETs.
In this study, the hopping conduction distance and bipolar switching properties of the Gd:SiOx thin film by (radio frequency, rf) rf sputtering technology for applications in RRAM devices were calculated and investigated. To discuss and verify the electrical switching mechanism in various different constant compliance currents, the typical current versus applied voltage (I-V) characteristics of gadolinium oxide RRAM devices was transferred and fitted. Finally, the transmission electrons’ switching behavior between the TiN bottom electrode and Pt top electrode in the initial metallic filament forming process of the gadolinium oxide thin film RRAM devices for low resistance state (LRS)/high resistance state (HRS) was described and explained in a simulated physical diagram model.
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