The recently emerged selective lateral epitaxy of semiconductor planar nanowires (NWs) via the vapor-liquid-solid (VLS) mechanism has redefined the long-standing symbolic image of VLS NW growth. The in-plane geometry and self-aligned nature make these planar NWs completely compatible with large scale manufacturing of NW-based integrated nanoelectronics. Here, we report on the realization of perfectly site-controlled growth of GaAs planar NW arrays with unity yield using lithographically defined gold (Au) seed dots. The growth rate of the planar NWs is found to decrease with the NW width at fixed spacing, which is consistent with the conventional VLS model based on the Gibbs-Thomson effect. It is found that in general, the planar and out-of-plane NW growth modes are both present. The yield of planar NWs decreases as their lateral dimension shrinks, and 100% yield of planar NWs can be achieved at moderate V/III ratios. Based on a study of the shape of seed particles, it is proposed that the adhesion between the liquid-phase seed particle and the substrate surface is important in determining the choice of growth mode. These studies represent advances in the fundamental understanding of the VLS planar NW growth mechanism and in the precise control of the planar NW site, density, width, and length for practical applications. In addition, high quality planar InAs NWs on GaAs (100) substrates is realized, verifying that the planar VLS growth mode can be extended to heteroepitaxy.

Wafer-scale defect-free planar III-V nanowire (NW) arrays with ∼100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

Existing theory and data cannot quantify the contribution of phonon drag to the Seebeck coefficient (S) in semiconductors at room temperature. We show that this is possible through comparative measurements between nanowires and the bulk. Phonon boundary scattering completely quenches phonon drag in silicon nanowires enabling quantification of its contribution to S in bulk silicon in the range 25-500 K. The contribution is surprisingly large (∼34%) at 300 K even at doping of ∼3 × 10(19) cm(-3). Our results contradict the notion that phonon drag is negligible in degenerate semiconductors at temperatures relevant for thermoelectric energy conversion. A revised theory of electron-phonon momentum exchange that accounts for a phonon mean free path spectrum agrees well with the data.

High-quality growth of planar GaAs nanowires (NWs) with widths as small as 35 nm is realized by comprehensively mapping the parameter space of group III flow, V/III ratio, and temperature as the size of the NWs scales down. Using a growth mode modulation scheme for the NW and thin film barrier layers, monolithically integrated AlGaAs barrier-all-around planar GaAs NW high electron mobility transistors (NW-HEMTs) are achieved. The peak extrinsic transconductance, drive current, and effective electron velocity are 550 μS/μm, 435 μA/μm, and ~2.9 × 10(7) cm/s, respectively, at 2 V supply voltage with a gate length of 120 nm. The excellent DC performance demonstrated here shows the potential of this bottom-up planar NW technology for low-power high-speed very-large-scale-integration (VLSI) circuits.

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