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Improvement of line edge roughness (LER) and line width roughness (LWR) is required for integration of semiconductor devices. This paper describes various process factors affecting LER/LWR of 193 nm resists such as mask layout (bright field/dark field), pitches, optical settings, substrates, film thickness, baking temperature and development condition. The origins of line roughness are discussed in view of aerial image contrast, transmittance of resists and pattern profiles. Bright field mask exhibited lower LER/LWR values than dark field mask, LER/LWR deteriorated as larger pitches and illumination condition affected roughness and these results are explained using normalized image log-slope (NILS). BARC dependence of line roughness is explained by pattern profile difference due to interactions between resist and BARC and in some cases BARC reflectivity. Contributions of film thickness, SB & PEB temperature and development condition to line roughness are also reported.

Developable BARCs (DBARCs) are useful for implant layers because they eliminate the plasma etch step avoiding damage to the plasma sensitive layers during implantation. It is expected that DBARC will also be used for non-implant layers and double exposure technology. AZ has pioneered DBARC based on photosensitive cleave as well as crosslink/decrosslink mechanisms. In this paper, we focus on various processing factors for 193nm DBARC and discuss the influences of prewet, thickness, topography and substrates on lithographic performance. Prewet of DBARC before resist coating deteriorated performance, however, it was resolved by modifying DBARC formulations. The optimized DBARC showed both optical and lithographic performance comparable to conventional BARCs. DBARCs minimized reflection from the substrates and notching of patterns was improved observed on silicon oxide topography. This paper includes simulation, DBARC contrast curve analyses, and recent dry and immersion exposure results of DBARC.

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