Radiation sensitive developable bottom anti-reflective coatings (DBARC): recent results

Houlihan, Francis M.; Dioses, Alberto; Kudo, Takanori; Li, Meng; Zhang, Lin; Vasanthan, Sumathy; Chakrapani, Srinivasan; Parthasarathy, Deepa; Antonio, Charito; Ng, Edward W.; Lu, Peng-Han; Neisser, Mark; Padmanaban, Munirathna

doi:10.1117/12.816375

Cited by 4 publications

(2 citation statements)

References 6 publications

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“…However, DUV lithography without BARC leads to serious problems in critical dimension (CD) control owing to the reflectivity change of substrate or resist footing attributable to chemical effects. [1][2][3] Moreover, implantation-level postpoly-gate patterning requires lithography instead of device topography. This presents additional challenges for lithography design in which the mask layout, illumination, and numerical aperture (NA) are determined.…”

Section: Introductionmentioning

confidence: 99%

Resist Residue in Ion Implantation Level Lithography

Ojima

Asano

Takahashi

et al. 2010

Jpn. J. Appl. Phys.

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We report the analysis of residual resist remaining after implantation level lithography on the topographical substrate. The problem experienced in a 45-nm-node complementary metal–oxide–semiconductor (CMOS) is described. From our experiment and simulation study, we found that switching exposure wavelength from argon fluoride (ArF) excimer lasers to krypton fluoride (KrF) excimer lasers ameliorates the issue of residual resist on gate stack substrates. In lithography over device stack such as gates, resolution cannot be explained by the Rayleigh equation's k 1. However, for the 32 nm node and below, ArF imaging has to be applied at ion implantation levels in view of the required resolution for a given mask layout. Therefore, we used a three-dimensional (3D) lithography simulator in order to clarify the mechanism of residual resist. From the analysis, the absorption of exposure light by sidewall materials is considered to be the reason for the residual resist. For the post-gate lithography at the ion implantation level, it is necessary to consider not only the resolution of the mask layout but the absorption of exposure light.

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Section: Introductionmentioning

confidence: 99%

Resist Residue in Ion Implantation Level Lithography

Ojima

Asano

Takahashi

et al. 2010

Jpn. J. Appl. Phys.

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“…Photosensitive DBARCs have photoimageable properties and resolve patterns irrespective of upper resist layer [9][10][11][12][13][14][15][16][17][18]. Therefore, they have better resolution and through-pitch performance which are required for logic devices and critical layers.…”

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confidence: 99%

PAG and Quencher Effects on DBARC Performance

Padmanaban

Kudo

Chakrapani

et al. 2011

J. Photopol. Sci. Technol.

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A novel method to reduce wafer topography effect for implant lithography process

Yuan

Bae

et al. 2010

SPIE Proceedings

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Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive investigation.

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Radiation sensitive developable bottom anti-reflective coatings (DBARC): recent results

Cited by 4 publications

References 6 publications

Resist Residue in Ion Implantation Level Lithography

Resist Residue in Ion Implantation Level Lithography

PAG and Quencher Effects on DBARC Performance

A novel method to reduce wafer topography effect for implant lithography process

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