The Bachet weight decomposition method is used to design a new 2D convolution-based filter, specifically aimed to image processing. The filter substitutes multipliers with simplified floating point adders to emulate standard 32 bit floating point multipliers, by using a set of pre-computed coefficients. A careful organization of the memory, together with the optimized distribution of the related hard macros in the FPGA fabric, allow the elaboration of the data in raster scan order, as those directly provided by an acquisition source, without the need of frame buffers or additional aligning circuitry. The proposed design achieves a state-of-the-art critical path delay of 4.7 ns on a Xilinx Virtex 7 FPGA
The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature
Exploiting the Bachet weight decomposition theorem, a new two-dimensional filter is designed. The filter can be adapted to different multimedia applications, but in this work it is specifically targeted to image processing applications. The method allows emulating standard 32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the exponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact implementation of a floating point filtering architecture when a fixed set of coefficients and a fixed range of input values are used. The elaboration of the data proceeds in raster-scan order and is capable of directly processing the data coming from the acquisition source thanks to a careful organization of the memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed architecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical path delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board
This paper presents the design of a new hardware accelerator, filtering the input data using Gabor functions and dedicated to image processing. The proposed design obtains a great reduction in terms of resources if compared to other state-of-The-Art implementations. This is done exploiting the separability of Gabor filters along certain orientations and through a reorganization of the arithmetic units and the memory structures, achieved thanks to the absence of frame buffers to store the entire input image and partially processed data. All the above reported features allow the design to obtain real-Time performances. The design has been targeted to a Xilinx Virtex 7 ASIC board and to CMOS 90nm std-cells, obtaining a minimum operating clock period of 5.8 ns for the FPGA implementation and of 2.9 ns for the std-cell one. The above reported results allow to process 83 and 168 1920Ã\u971080 pixels (Full-HD) frame-per-second, respectively
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