Design of a Gabor Filter HW Accelerator for Applications in Medical Imaging

Licciardo, Gian Domenico; Cappetta, Carmine; Benedetto, Luigi Di

doi:10.1109/tcpmt.2018.2818947

Cited by 14 publications

(6 citation statements)

References 31 publications

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“…Finally, to demonstrate the advantages of the proposed solution in real-time image processing, SR-MAC has been used to replace the arithmetic operators in 34 and. 35 In, 34 a HW accelerator of a CNN is used for real-time recognition of human postures on an Artix 7 FPGA, by employing an image processing approach. 35 implements a circuit for real-time Gabor filtering o f i mages o n a V irtex 7 F PGA.…”

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

“…35 In, 34 a HW accelerator of a CNN is used for real-time recognition of human postures on an Artix 7 FPGA, by employing an image processing approach. 35 implements a circuit for real-time Gabor filtering o f i mages o n a V irtex 7 F PGA. R elative t o 34 ( 35 ), t he i ntroduction o f our system reduces the number of mapped FFs by 6% (4.9%) and P dynN by 14% (3.1%), while increasing f Max by 14% (3%).…”

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

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Self-adapting reconfigurable multiply-accumulator for real-time image processing in embedded systems

Fasolino,

Vitolo,

Liguori

et al. 2024

Real-Time Processing of Image, Depth, and Video Information 2024

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Multiply-Accumulate (MAC) operation is widely used in various real-time image processing tasks, ranging from Convolutional Neural Networks to digital filtering, significantly impacting overall system performance. In this work the Self-Adapting Reconfigurable Multiply-Accumulate (SR-MAC) is proposed as a new instrument to find the optimal trade-off between operation throughput, power consumption and physical resources utilization in real-time image processing applications. Operations of the proposed system rely on the dynamic reconfiguration of the hardware resources on the basis of the current computational requirements. This is achieved by monitoring overflow and over-representation occurrences at each accumulation cycle, and properly considering the relevant portion of the accumulation result. A custom architecture of the proposed algorithm has been designed and implemented on an AMD Xilinx Artix-7 FPGA through a Verilog description and compared to the AMD Xilinx fixed-point macro (floating-point fused multiply-accumulate). The SR-MAC achieves reductions of 83% (82%), 79% (93%) and 87.2% (94%) in the number of LUTs, FFs, and the power dissipation, P dynN , respectively. The SR-MAC has also been used to replace arithmetic units in typical real-time image processing applications. In these cases, its employment has allowed the reduction up to 6% and 14% of FFs and P dynN , respectively, while increasing up to 14% the f M ax . These results highlight the significant performance enhancement achieved with respect to both single operators and entire systems, making SR-MAC an excellent design choice in real-time image processing applications.

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Section: Implementation Results and Comparisonsmentioning

confidence: 99%

Section: Implementation Results and Comparisonsmentioning

confidence: 99%

Self-adapting reconfigurable multiply-accumulator for real-time image processing in embedded systems

Fasolino,

Vitolo,

Liguori

et al. 2024

Real-Time Processing of Image, Depth, and Video Information 2024

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“…However, RNS to BNS conversion operation is very resource-intensive, partially neutralizes the device performance gain, and greatly affects the hardware resources. This approach is advisable for medical imaging applications with performance-priority devices [43]. The developed FPGA accelerators are cheap, practical, and can be introduced into the mass market.…”

Section: B Hardware Implementations Results Of Medical Image Wp With ...mentioning

confidence: 99%

“…The prototype of the first portable 3D digital ultrasonic back-end system implemented in FPGA is designed in [42]. The authors [43] presented the Gabor filter design on the FPGA accelerator for power-efficient and high-performance medical imaging applications. FPGA-based emulation of minimum variance distortionless response beamformer architecture for ultrasound imaging is proposed in [44].…”

Section: B Hardware Accelerators For Medical Image Processingmentioning

confidence: 99%

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

et al. 2022

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Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (fieldprogrammable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.INDEX TERMS Medical image processing, discrete wavelet transform, scaled filter coefficients, residue number system, high-performance computing, hardware accelerator, field-programmable gate arrays.

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“…With the usage of separability, the design of this layer is achieved more efficiently in both resource consumption and clock speed, compared with previously published designs. As shown in [12, 29], the Gabor filter is separable in 0°, 45°, 90°, and 135° orientations, provided that the Gaussian weighting function is changed to an isotropic function by specifying γ = 1. So far, much research has been conducted to decrease the computation complexity of the Gabor filter.…”

Section: Hardware Architecturementioning

confidence: 99%

Modification and hardware implementation of cortex‐like object recognition model

et al. 2020

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Design of a Gabor Filter HW Accelerator for Applications in Medical Imaging

Cited by 14 publications

References 31 publications

Self-adapting reconfigurable multiply-accumulator for real-time image processing in embedded systems

Self-adapting reconfigurable multiply-accumulator for real-time image processing in embedded systems

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

Modification and hardware implementation of cortex‐like object recognition model

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