Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. Large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx Block-RAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080×1920) @103 fps.

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An FPGA-Based Simple RGB-HSI Space Conversion Algorithm for Hardware Image Processing

Zhi

Cui

Deng

et al. 2020

IEEE Access

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In this paper, a new, low-complexity, easy-to-implement hardware method for color space conversion between the red-green-blue (RGB) and the hue-saturation-intensity (HSI) color spaces called the simple RGB-HSI space conversion (S-SC) algorithm is proposed, which aims to provide more rapid computing due to the need for fewer operations. In the S-SC algorithm, we reconstruct the model of space conversion between the RGB color space and the HSI color space (RGB-HSI) by inverting the conversion from the HSI color space to the RGB color space of the traditional geometric derivation algorithm. As a result, the nonlinear model-realized RGB-HSI color space conversion by the geometric derivation algorithm is transformed into a linear conversion model, which can avoid complicated calculations such as trigonometric and inverse trigonometric functions in the color space conversion process. The model can effectively reduce the computational complexity of the algorithm and facilitate hardware implementation at the same time. To evaluate the performance of the S-SC algorithm, we first compare the S-SC algorithm with the geometric derivation algorithm from the computational complexity perspective. On this basis, we compare the S-SC algorithm with five other RGB-HSI color space conversion algorithms from the perspectives of error and conversion effect. Finally, we use the field programmable gate array (FPGA) hardware platform to analyze and verify the timing sequence and logical resource consumption and verify the effectiveness of the proposed algorithm with experimental results. We show that the S-SC algorithm achieves good performance in terms of conversion accuracy, logical unit resource occupancy, and output timing.

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Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

Cited by 7 publications

References 22 publications

A 0.8 mW TinyML-Based PDM-to-PCM Conversion for In-Sensor KWS Applications

A 0.8 mW TinyML-Based PDM-to-PCM Conversion for In-Sensor KWS Applications

Resource-Efficient Image Buffer Architecture for Neighborhood Processors

An FPGA-Based Simple RGB-HSI Space Conversion Algorithm for Hardware Image Processing

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