FPGA optimization of convolution-based 2D filtering processor for image processing

Licciardo, Gian Domenico; Cappetta, Carmine; Benedetto, Luigi Di

doi:10.1109/ceec.2016.7835910

Cited by 17 publications

(7 citation statements)

References 20 publications

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“…At last, the critical path delay, pixel access rate, power consumption, and resource utilization of the proposed Reduced-Access Pipelined Convolver (RAPC) are compared by a conventional Non-Pipelined Convolver (NPC). Also, the authors of [5] have optimized the FPGA implementation of a convolution-based 2D filtering processor for image processing applications. The proposed filter swaps the multiplication unit with floating-point adders and also exploits a set of pre-computed coefficients to design a 32-bit multiplier module.…”

Section: Related Workmentioning

confidence: 99%

“…Let's consider 'i' as the index of the row and 'j' as the index of the column. Therefore, if we suppose that pixels in a row are in a narrow range (not fixed) then Equation (3) will be modified to Equation (5):…”

Section: Computational Analysismentioning

confidence: 99%

“…In this architecture, a row or column of the input pixels is registered. Then, based on Equations ( 3), (5), and (7) the average of all input pixels in a window, row, or column is computed respectively. To implement the pipeline processing, the average value is stored before sending it to the proposed approximate convolver.…”

Section: Real-time Approximate Convolvermentioning

confidence: 99%

“…To show the superiority of the proposed design, we have also compared it with other related 2D convolvers. As shown in Table 1, the pixel access rate, and resource utilization of the convolvers proposed in [5], [6], and [19] are compared with approximate and combined convolvers. In this discussion, the FPGA devices are altered to make a fair comparison with other designs.…”

Section: Resource Utilizationmentioning

confidence: 99%

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Real-time approximate and combined 2D convolvers for FPGA-based image processing

et al. 2023

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Convolution widely has been used as the main part of the improvement in digital image processing applications. In convolutional computations, a large number of memory accesses and a huge amount of computations challenge its performance. Many of the related proposed convolvers are based on exact computations. Although exact convolvers keep the accuracy of the convolution operation at the top level, sometimes by missing a negligible amount of accuracy, the performance can be improved. Approximate computing is a new technique for solving computation overhead problems. In this paper, approximate 2D convolvers are presented which minimize the memory access rate and computations by a special factor of Multiply-and-Accumulate (MAC) terms. On the other hand, to preserve the flexibility for supporting different required accuracy, the proposed approximate convolvers are combined with the exact designs with real-time pre-processing stages by exploiting innovative methods which manage the hardware overhead. In comparison to conventional convolvers, the proposed designs improve the number of active resources which causes a significant reduction in power consumption. For 3 × 3 kernel size, the evaluation results on the Xilinx Virtex-7 (XC7V2000t) FPGA device show 34% and 20% power optimization of the proposed approximate and combined convolvers respectively, in comparison to Exact Convolver (EC). Also, this improvement grows by increasing the kernel size. Finally, a comparison based on RMSE and PSNR for different sample images and filters reveals that the error rate and image quality reduction are acceptable for many real-time image processing applications.

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Section: Related Workmentioning

confidence: 99%

Section: Computational Analysismentioning

confidence: 99%

Section: Real-time Approximate Convolvermentioning

confidence: 99%

Section: Resource Utilizationmentioning

confidence: 99%

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Real-time approximate and combined 2D convolvers for FPGA-based image processing

et al. 2023

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“…Local data reuse has been enhanced in the proposed architecture by an intensive use of FIFO memories. Moreover, weight binarization allows to reduce the MAC operations to ADD/SUB operations, with a significant reduction of mapped resources [27]- [29]. The block diagram of the HNN accelerator is shown in Fig.…”

Section: B Hnn Acceleratormentioning

confidence: 99%

Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

Vita

Pau

Benedetto

et al. 2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. Aiming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.

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Low-Power Integrated Circuit for Orientation Independent Acquisitions from Smart Accelerometers

Vita

Licciardo

Femia

et al. 2020

Lecture Notes in Electrical Engineering

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FPGA optimization of convolution-based 2D filtering processor for image processing

Cited by 17 publications

References 20 publications

Real-time approximate and combined 2D convolvers for FPGA-based image processing

Real-time approximate and combined 2D convolvers for FPGA-based image processing

Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems

Low-Power Integrated Circuit for Orientation Independent Acquisitions from Smart Accelerometers

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